Error detection method
An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).
- Research Organization:
- NVO (Nevada Field Office, Las Vegas, NV (United States))
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- DMS-9902360
- Assignee:
- Board of Regents of the Nevada System of Higher Education (Reno, NV)
- Patent Number(s):
- 8,464,143
- Application Number:
- 12/657,025
- OSTI ID:
- 1084198
- Country of Publication:
- United States
- Language:
- English
Similar Records
Concurrent error detection using watchdog processors - A survey
MO-FG-202-07: Real-Time EPID-Based Detection Metric For VMAT Delivery Errors