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Title: Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

Patent ·
OSTI ID:1039559
 [1];  [2];  [3];  [4];  [2];  [5];  [6];  [7]
  1. Ridgefield, CT
  2. Rochester, MN
  3. Mount Kisco, NY
  4. Irvington, NY
  5. Cortlandt Manor, NY
  6. Leander, TX
  7. Yorktown Heights, NY
+ Show Author Affiliations

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,140,925
Application Number:
11/768,791
OSTI ID:
1039559
Resource Relation:
Patent File Date: 2007 Jun 26
Country of Publication:
United States
Language:
English

References (8)

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Performance evaluation of adaptive MPI
  • Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06 https://doi.org/10.1145/1122971.1122976
conference January 2006
Directory-based cache coherence in large-scale multiprocessors journal June 1990
Synchronization, coherence, and event ordering in multiprocessors journal February 1988
Overview of the Blue Gene/L system architecture journal March 2005
Optimization of MPI collective communication on BlueGene/L systems conference January 2005
Intel 870: a building block for cost-effective, scalable servers journal March 2002
Blue Gene/L advanced diagnostics environment journal March 2005

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