Static power reduction for midpoint-terminated busses
Patent
·
OSTI ID:1013026
- Yorktown Heights, NY
- Brewster, NY
A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B 554331
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 7,873,843
- Application Number:
- 11/768,552
- OSTI ID:
- 1013026
- Country of Publication:
- United States
- Language:
- English
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