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Title: System for processing an encrypted instruction stream in hardware

Patent ·
OSTI ID:1246889

A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data. A central processing unit (CPU) is operatively coupled to the main memory. A decryptor is operatively coupled to the main memory and located within the CPU. The decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core. Unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal.

Research Organization:
Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC05-76RL01830
Assignee:
BATTELLE MEMORIAL INSTITUTE (Richland, WA)
Patent Number(s):
9,311,493
Application Number:
13/954,487
OSTI ID:
1246889
Resource Relation:
Patent File Date: 2013 Jul 30
Country of Publication:
United States
Language:
English

References (7)

Countering code-injection attacks with instruction-set randomization
  • Kc, Gaurav S.; Keromytis, Angelos D.; Prevelakis, Vassilis
  • CCS '03 Proceedings of the 10th ACM conference on Computer and communications security, p. 272-280 https://doi.org/10.1145/948109.948146
conference January 2003
A Fully Homomorphic Crypto-Processor Design book January 2013
Crypto microprocessor that executes enciphered programs patent August 1984
RISC computer with unaligned reference handling and method for the same patent March 1989
In-line decryption for protecting embedded software patent February 2002
Preventing stack buffer overflow attacks patent August 2006
Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values patent May 2014