Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)
A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
- Research Organization:
- International Business Marchines Corporation, Armonk, NY, USA
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B554331
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,640,070
- Application Number:
- 12/941,834
- OSTI ID:
- 1117859
- Resource Relation:
- Patent File Date: 2010 Nov 08
- Country of Publication:
- United States
- Language:
- English
System on a chip FPGA spatial debugging using single snapshot
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