Bipartite memory network architectures for parallel processing
- Illinois Univ., Urbana, IL (United States). Dept. of Computer Science
Parallel architectures are boradly classified as either shared memory or distributed memory architectures. In this paper, the authors propose a third family of architectures, called bipartite memory network architectures. In this architecture, processors and memory modules constitute a bipartite graph, where each processor is allowed to access a small subset of the memory modules, and each memory module allows access from a small set of processors. The architecture is particularly suitable for computations requiring dynamic load balancing. The authors explore the properties of this architecture by examining the Perfect Difference set based topology for the graph. Extensions of this topology are also suggested.
- OSTI ID:
- 5123927
- Country of Publication:
- United States
- Language:
- English
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