Simulation of bus architectures for multiprocessor systems
Book
·
OSTI ID:6153056
The authors present the results of the simulation of three different bus architectures used in multiprocessor systems. The timeshared bus, multibus, and cross bar switch configurations are modeled. Activity diagrams are used as a basis to develop the models. Since the models are based upon hypothetical multiprocessor systems, there is no way to compare the models performance with actual hardware performance. Therefore, independent models are developed in both FORTRAN and Pascal to validate the results. Each model contains a number of functional units, i.e. memory modules (MM), central processing units (CPUs), and input/output processors (IOPs), connected by a particular bus configuration. The results of the simulations are presented as a series of graphs that display average percentage utilization curves for a particular module class, such as CPUs, as a function of some independent variable such as I/O request rate. The results of some of the simulations are compared with similar results published by other authors. 8 references.
- OSTI ID:
- 6153056
- Country of Publication:
- United States
- Language:
- English
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