Hysteresis modeling in graphene field effect transistors

Journal Article · Sat Feb 21 00:00:00 EST 2015 · Journal of Applied Physics

DOI:https://doi.org/10.1063/1.4913209· OSTI ID:22413135

Winters, M.; Rorsman, N. ^[1]; Sveinbjörnsson, E. Ö. ^[2]

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1. Department of Microtechnology and Nanoscience, Chalmers University of Technology, 412-96 Göteborg (Sweden)
2. Science Institute, University of Iceland, IS-107 Reykjavik (Iceland)

Graphene field effect transistors with an Al{sub 2}O{sub 3} gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage v{sub g} versus the drain current i{sub d} reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi energy. The electron transport equations are then used to calculate the drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via a modified Preisach kernel.

• OSTI ID: 22413135
• Journal Information: Journal of Applied Physics, Vol. 117, Issue 7; Other Information: (c) 2015 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0021-8979
• Country of Publication: United States
• Language: English

Related Subjects

75 CONDENSED MATTER PHYSICS
SUPERCONDUCTIVITY AND SUPERFLUIDITY
ALUMINIUM OXIDES
CHEMICAL VAPOR DEPOSITION
CLATHRATES
DIELECTRIC MATERIALS
ELECTRIC POTENTIAL
ELECTRONS
FIELD EFFECT TRANSISTORS
GRAPHENE
HYSTERESIS
LAYERS
SILICON CARBIDES
TRANSPORT THEORY