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Title: Critical dimension and pattern size enhancement using pre-strained lithography

This paper proposes a non-wavelength-shortening-related critical dimension and pattern size reduction solution for the integrated circuit industry that entails generating strain on the substrate prior to lithography. Pattern size reduction of up to 49% was achieved regardless of shape, location, and size on the xy plane, and complete theoretical calculations and process steps are described in this paper. This technique can be applied to enhance pattern resolution by employing materials and process parameters already in use and, thus, to enhance the capability of outdated lithography facilities, enabling them to particularly support the manufacturing of flexible electronic devices with polymer substrates.
Authors:
 [1] ;  [2] ;  [1] ;  [3]
  1. Department of Power Mechanical Engineering, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsin Chu 30013, Taiwan (China)
  2. Institute of NanoEngineering and MicroSystems, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsin Chu 30013, Taiwan (China)
  3. (China)
Publication Date:
OSTI Identifier:
22350933
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 105; Journal Issue: 15; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; ELECTRONIC EQUIPMENT; INTEGRATED CIRCUITS; MANUFACTURING; POLYMERS; RESOLUTION; STRAINS; SUBSTRATES; WAVELENGTHS