Performance Enhancement of PFET Planar Devices by Plasma Immersion Ion Implantation (P3I)
- IMEC, Kapeldreef 75, 3001 Leuven (Belgium)
- Applied Materials, 974 E. Arques Avenue, Sunnyvale, CA (United States)
- Also IKS-Dept. Physics, KULeuven (Belgium)
A study of doping the pMOS Lightly Doped Drain (LDD) by Plasma Immersion Ion Implantation (P3i) with BF3 is presented which demonstrates a better transistor performance compared to standard beam line Ion Implantation (I/I). The benefit of P3i comes from the broad angular distribution of the impinging ions thereby doping the poly-silicon gate sidewall as well. Gate capacitance of short channel devices has been measured and clearly shows this improvement. This model is clearly supported by high resolution 2D-carrier profiles using Scanning Spreading Resistance Microscopy (SSRM) which shows this gate sidewall doping. The broad angular distribution also implies a smaller directional sensitivity (to for instance the detailed gate edge shape) and leads to devices which are perfectly balanced, when Source and Drain electrode are switched.
- OSTI ID:
- 21251705
- Journal Information:
- AIP Conference Proceedings, Vol. 1066, Issue 1; Conference: 17. international conference on ion implantation technology, Monterey, CA (United States), 8-13 Jun 2008; Other Information: DOI: 10.1063/1.3033663; (c) 2008 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0094-243X
- Country of Publication:
- United States
- Language:
- English
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