Increasing throughput of multiplexed electrical bus in pipe-lined architecture

Asaad, Sameh; Brezzo, Bernard V; Kapur, Mohit

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Title: Increasing throughput of multiplexed electrical bus in pipe-lined architecture

Abstract

Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

Inventors:: Asaad, Sameh; Brezzo, Bernard V; Kapur, Mohit

Issue Date:: Tue May 27 00:00:00 EDT 2014

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1132572

Patent Number(s):: 8737233

Application Number:: 13/236,109

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F13/4059 - {where the synchronisation uses buffers, e.g. for speed matching between buses}

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L12/28 - characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
H04L12/66 - Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
H04L43/00 - {Arrangements for monitoring or testing packet switching networks

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 Sep 19

Country of Publication:: United States

Language:: English

Subject:: 46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY

Citation Formats


                    Asaad, Sameh, Brezzo, Bernard V, and Kapur, Mohit. Increasing throughput of multiplexed electrical bus in pipe-lined architecture.  United States: N. p., 2014. 
        Web.

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                    Asaad, Sameh, Brezzo, Bernard V, & Kapur, Mohit. Increasing throughput of multiplexed electrical bus in pipe-lined architecture.  United States.

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                    Asaad, Sameh, Brezzo, Bernard V, and Kapur, Mohit. Tue .  
        "Increasing throughput of multiplexed electrical bus in pipe-lined architecture".  United States.  https://www.osti.gov/servlets/purl/1132572.

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@article{osti_1132572,

  title        = {Increasing throughput of multiplexed electrical bus in pipe-lined architecture},

  author       = {Asaad, Sameh and Brezzo, Bernard V and Kapur, Mohit},

  abstractNote = {Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue May 27 00:00:00 EDT 2014},

  month        = {Tue May 27 00:00:00 EDT 2014}

}

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Works referencing / citing this record:

Multi-FPGA prototyping of an ASIC circuit
patent, July 2016

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Similar Records

Title: Increasing throughput of multiplexed electrical bus in pipe-lined architecture

Abstract

Citation Formats

Pipelined digital CPU with deadlock resolution patent, April 1991

Structure and method of performing DMA transfers between memory and I/O devices utilizing a single DMA controller within a notebook and docking station computer system patent, February 1999

Integrated multiport switch having management information base (MIB) interface temporary storage patent, October 2000

Communication device, multiple bus control device and LSI for controlling multiple bus patent, December 2002

Functional verification of integrated circuit designs patent, September 2003

Mesh architecture for synchronous cross-connects patent, September 2006

On-chip shared memory based device architecture patent, June 2010

Adaptive execution cycle control method for enhanced instruction throughput patent, May 2011

High density optical source bank patent-application, September 2002

Clock generation systems and methods patent-application, June 2005

Behavior processor system and method patent-application, June 2006

Multi-Channel Synchronization Architecture patent-application, January 2007

Request processing between failure windows patent-application, February 2007

Hardware acceleration system for simulation of logic and memory patent-application, June 2007

Method and device for transmitting data over a plurality of transmission lines patent-application, July 2007

Hardware-based HDL code coverage and design analysis patent-application, August 2007

Adaptive Frequency Control Method for Enhanced Instruction Throughput patent-application, January 2009

Cross-Bar Switching in an Emulation Environment patent-application, July 2009

FPGA Simulated Annealing Accelerator patent-application, December 2009

Control Component for Controlling a Delay Interval Within a Memory Component patent-application, March 2011

Multi-FPGA prototyping of an ASIC circuit patent, July 2016

Pipelined digital CPU with deadlock resolution
patent, April 1991

Structure and method of performing DMA transfers between memory and I/O devices utilizing a single DMA controller within a notebook and docking station computer system
patent, February 1999

Integrated multiport switch having management information base (MIB) interface temporary storage
patent, October 2000

Communication device, multiple bus control device and LSI for controlling multiple bus
patent, December 2002

Functional verification of integrated circuit designs
patent, September 2003

Mesh architecture for synchronous cross-connects
patent, September 2006

On-chip shared memory based device architecture
patent, June 2010

Adaptive execution cycle control method for enhanced instruction throughput
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High density optical source bank
patent-application, September 2002

Clock generation systems and methods
patent-application, June 2005

Behavior processor system and method
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Multi-Channel Synchronization Architecture
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Request processing between failure windows
patent-application, February 2007

Hardware acceleration system for simulation of logic and memory
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Method and device for transmitting data over a plurality of transmission lines
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Hardware-based HDL code coverage and design analysis
patent-application, August 2007

Adaptive Frequency Control Method for Enhanced Instruction Throughput
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Cross-Bar Switching in an Emulation Environment
patent-application, July 2009

FPGA Simulated Annealing Accelerator
patent-application, December 2009

Control Component for Controlling a Delay Interval Within a Memory Component
patent-application, March 2011

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