Time-division multiplexing data bus
Abstract
A two-to-one multiplexor comprises a first data input configured to hold data provided from a first preceding asynchronous pipeline stage and a second data input configured to hold data provided from a second preceding asynchronous pipeline stage, a 4-phase bundled data protocol facilitating communication between the first and the second data inputs and the first and second preceding asynchronous pipeline stage, an arbitration unit connected to the first data input and the second data input, and configured to select which of the data from the first and the second data inputs is released, a request release unit, and a reset unit wherein the arbitration unit, the request release unit, and the reset unit implement and complete a second 4-phase bundled data protocol facilitating communication with a succeeding asynchronous pipeline stage for transmission of the data chosen by the arbitration unit thereby providing asynchronous multiplexing of the data.
- Inventors:
- Issue Date:
- Research Org.:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532072
- Patent Number(s):
- 9928202
- Application Number:
- 15/134,520
- Assignee:
- Fermi Research Alliance, LLC (Batavia, IL)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC02-07CH11359
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016-04-21
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Hoff, James R. Time-division multiplexing data bus. United States: N. p., 2018.
Web.
Hoff, James R. Time-division multiplexing data bus. United States.
Hoff, James R. Tue .
"Time-division multiplexing data bus". United States. https://www.osti.gov/servlets/purl/1532072.
@article{osti_1532072,
title = {Time-division multiplexing data bus},
author = {Hoff, James R.},
abstractNote = {A two-to-one multiplexor comprises a first data input configured to hold data provided from a first preceding asynchronous pipeline stage and a second data input configured to hold data provided from a second preceding asynchronous pipeline stage, a 4-phase bundled data protocol facilitating communication between the first and the second data inputs and the first and second preceding asynchronous pipeline stage, an arbitration unit connected to the first data input and the second data input, and configured to select which of the data from the first and the second data inputs is released, a request release unit, and a reset unit wherein the arbitration unit, the request release unit, and the reset unit implement and complete a second 4-phase bundled data protocol facilitating communication with a succeeding asynchronous pipeline stage for transmission of the data chosen by the arbitration unit thereby providing asynchronous multiplexing of the data.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {3}
}
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Works referenced in this record:
Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
patent, October 2014
- Gill, Gennette Delaine; Singh, Montek
- US Patent Document 8,872,544
Asynchronous digital circuits including arbitration and routing primatives for asynchronous and mixed-timing networks
patent, July 2014
- Nowick, Steven M.; Horak, Michael; Carlberg, Matthew
- US Patent Document 8,766,667
Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks
patent, January 2013
- Nowick, Steven M.; Horak, Michael; Carlberg, Matthew
- US Patent Document 8,362,802
Asynchronous switch based on butterfly fat-tree for network on chip application
patent-application, December 2005
- Kang, Min-Chang; Jung, Eun-Gu; Har, Dong-Soo
- US Patent Application 11/023087; 20050271054
Method and device for initialising an asynchronous latch chain
patent-application, November 2002
- Marx, Thilo; Schrogmeier, Peter
- US Patent Application 10/135686; 20020176447
Universal pipeline latch for mousetrap logic circuits
patent, February 1995
- Yetter, Jeffry D.
- US Patent Document 5,392,423
Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock
patent-application, November 2002
- Marx, Thilo; Schrogmeier, Peter
- US Patent Application 10/143600; 20020178392
Delay Insensitive Data Transfer Apparatus with Low Power Consumption
patent-application, May 2008
- Oh, Myeong-Hoon; Kim, Seong-Woon; Kim, Myung-Joon
- US Patent Application 11/927972; 20080123765
Asynchronous Pipeline System, Stage, and Data Transfer Mechanism
patent-application, April 2012
- Oh, Myeong-Hoon; Kim, Young Woo; Kim, Sung Nam
- US Patent Application 13/278385; 20120102300
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines
journal, June 2007
- Singh, M.; Nowick, S. M.
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, Issue 6
Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
patent, March 2014
- Gill, Gennette Delaine; Singh, Montek
- US Patent Document 8,669,779
Source Asynchronous Signaling
patent-application, March 2014
- Stevens, Kenneth Scott; Das, Shomit
- US Patent Application 13/829243; 20140064096
Asynchronous pipeline with latch controllers
patent, October 2005
- Singh, Montek; Nowick, Steven M.
- US Patent Document 6,958,627
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
journal, April 2011
- Horak, Michael N.; Nowick, Steven M.; Carlberg, Matthew
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Issue 4
An analog VLSI chip with asynchronous interface for auditory feature extraction
journal, May 1998
- Kumar, N.; Himmelbauer, W.; Cauwenberghs, G.
- IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, Issue 5
FPHX: A new silicon strip readout chip for the PHENIX experiment at RHIC
conference, October 2009
- Hoff, J. R.; Zimmerman, T. N.; Yarema, R. J.
- 2009 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2009), 2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)
Wrapper Circuit for Globally Asynchronous Locally Synchronous System and Method for Operating the Same
patent-application, June 2009
- Oh, Myeong-Hoon; Kim, Seong-Woon; Kim, Myung-Joon
- US Patent Application 12/186114; 20090150706
Fermilab silicon strip readout chip for BTeV
journal, June 2005
- Yarema, R.; Hoff, J.; Mekkaoui, A.
- IEEE Transactions on Nuclear Science, Vol. 52, Issue 3
MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelines
conference, January 2001
- Singh, M.; Nowick, S. M.
- 2001 International Conference on Computer Design. ICCD 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
Apparatus and method for fairness arbitration for a shared pipeline in a large SMP computer system
patent, March 2010
- Dunn, Deanna P.; Jones, Christine C.; O'Neill, Arthur J.
- US Patent Document 7,685,345
FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors
journal, August 2006
- Re, V.; Manghisoni, M.; Ratti, L.
- IEEE Transactions on Nuclear Science, Vol. 53, Issue 4
Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock
patent-application, July 2006
- Marx, Thilo; Schrogmeier, Peter
- US Patent Application 11/367218; 20060149989