Tier identification (TID) for tiered memory characteristics

Chang, Jichuan; Lim, Kevin T; Ranganathan, Parthasarathy

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Title: Tier identification (TID) for tiered memory characteristics

Abstract

A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.

Inventors:: Chang, Jichuan; Lim, Kevin T; Ranganathan, Parthasarathy

Issue Date:: Tue Mar 25 00:00:00 EDT 2014

Research Org.:: Hewlett-Packard Development Company, L.P, Houston, TX, USA

Sponsoring Org.:: USDOE

OSTI Identifier:: 1128534

Patent Number(s):: 8683125

Application Number:: 13/286,681

Assignee:: Hewlett-Packard Development Company, L.P. (Houston, TX)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/10 - Address translation
G06F2212/205 - Hybrid memory, e.g. using both volatile and non-volatile memory
G06F9/5016 - {the resource being the memory}

Show less

DOE Contract Number:: SC0005026

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Chang, Jichuan, Lim, Kevin T, and Ranganathan, Parthasarathy. Tier identification (TID) for tiered memory characteristics.  United States: N. p., 2014. 
        Web.

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                    Chang, Jichuan, Lim, Kevin T, & Ranganathan, Parthasarathy. Tier identification (TID) for tiered memory characteristics.  United States.

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                    Chang, Jichuan, Lim, Kevin T, and Ranganathan, Parthasarathy. Tue .  
        "Tier identification (TID) for tiered memory characteristics".  United States.  https://www.osti.gov/servlets/purl/1128534.

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@article{osti_1128534,

  title        = {Tier identification (TID) for tiered memory characteristics},

  author       = {Chang, Jichuan and Lim, Kevin T and Ranganathan, Parthasarathy},

  abstractNote = {A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Mar 25 00:00:00 EDT 2014},

  month        = {Tue Mar 25 00:00:00 EDT 2014}

}

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Works referenced in this record:

Indexing management for hierarchical main memory
patent, July 2004

Zhang, Nick
US Patent Document 6,763,347
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6763347

Method for measuring memory latency in a hierarchical memory system
patent, May 2006

Le, Hung Q.; Mericas, Alexander Erik; Mirabella, Robert Dominick
US Patent Document 7,051,177
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Tiered secondary memory architecture to reduce power consumption in a portable computer system
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Tsirkel, Aaron; Kardach, James P.
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Method to support heterogeneous memories
patent, March 2010

Zimmer, Vincent J.; Rothman, Michael A.
US Patent Document 7,685,376
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Memory power and performance management
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Sokolov, Dotan; Shalvi, Ofir
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System and method for allocating system resources
patent-application, February 2005

Gipp, Stephan Kurt
US Patent Application 10/643740; 20050044547
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Advanced dynamic disk memory module special operations
patent-application, June 2007

Bonella, Randy M.; Lam, Chung W.
US Patent Application 11/635926; 20070136523
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Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
patent-application, August 2007

Tran, Thang
US Patent Application 11/466621; 20070204137
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Snoop-Based Prefetching
patent-application, February 2010

Bell, Gordon Bernard; Davis, Gordon Taylor; Derby, Jeffrey Haskell
US Patent Application 12/192072; 20100042786
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100042786

Method for Managing an Embedded System to Enhance Performance Thereof, and Associated Embedded System
patent-application, February 2011

Chiang, Ying-Chieh; Lin, Wei-Hsien
US Patent Application 12/511040; 20110029735
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110029735

Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller
patent-application, June 2011

Tremaine, Robert B.; Wisniewski, Robert W.
US Patent Application 12/649856; 20110161597
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110161597

Low overhead concurrency control for partitioned main memory databases
conference, January 2010

Jones, Evan P. C.; Abadi, Daniel J.; Madden, Samuel
Proceedings of the 2010 international conference on Management of data - SIGMOD '10
https://doi.org/10.1145/1807167.1807233

Disaggregated memory for expansion and sharing in blade servers
journal, June 2009

Lim, Kevin; Chang, Jichuan; Mudge, Trevor
ACM SIGARCH Computer Architecture News, Vol. 37, Issue 3
https://doi.org/10.1145/1555815.1555789

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Similar Records

Title: Tier identification (TID) for tiered memory characteristics

Abstract

Citation Formats

Indexing management for hierarchical main memory patent, July 2004

Method for measuring memory latency in a hierarchical memory system patent, May 2006

Tiered secondary memory architecture to reduce power consumption in a portable computer system patent, August 2006

Method to support heterogeneous memories patent, March 2010

Memory power and performance management patent, April 2011

System and method for allocating system resources patent-application, February 2005

Advanced dynamic disk memory module special operations patent-application, June 2007

Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture patent-application, August 2007

Snoop-Based Prefetching patent-application, February 2010

Method for Managing an Embedded System to Enhance Performance Thereof, and Associated Embedded System patent-application, February 2011

Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller patent-application, June 2011

Low overhead concurrency control for partitioned main memory databases conference, January 2010

Disaggregated memory for expansion and sharing in blade servers journal, June 2009

Indexing management for hierarchical main memory
patent, July 2004

Method for measuring memory latency in a hierarchical memory system
patent, May 2006

Tiered secondary memory architecture to reduce power consumption in a portable computer system
patent, August 2006

Method to support heterogeneous memories
patent, March 2010

Memory power and performance management
patent, April 2011

System and method for allocating system resources
patent-application, February 2005

Advanced dynamic disk memory module special operations
patent-application, June 2007

Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
patent-application, August 2007

Snoop-Based Prefetching
patent-application, February 2010

Method for Managing an Embedded System to Enhance Performance Thereof, and Associated Embedded System
patent-application, February 2011

Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller
patent-application, June 2011

Low overhead concurrency control for partitioned main memory databases
conference, January 2010

Disaggregated memory for expansion and sharing in blade servers
journal, June 2009