Memory instruction for memory tiers
Abstract
Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.
- Inventors:
- Issue Date:
- Research Org.:
- Micron Technology, Inc., Boise, ID (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 2293766
- Patent Number(s):
- 11797198
- Application Number:
- 17/238,791
- Assignee:
- Micron Technology, Inc. (Boise, ID)
- DOE Contract Number:
- 4000165069
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 04/23/2021
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Roberts, David Andrew. Memory instruction for memory tiers. United States: N. p., 2023.
Web.
Roberts, David Andrew. Memory instruction for memory tiers. United States.
Roberts, David Andrew. Tue .
"Memory instruction for memory tiers". United States. https://www.osti.gov/servlets/purl/2293766.
@article{osti_2293766,
title = {Memory instruction for memory tiers},
author = {Roberts, David Andrew},
abstractNote = {Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {10}
}
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