General purpose programmable accelerator board
Abstract
A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.
- Inventors:
-
- Albuquerque, NM
- Edgewood, NM
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- OSTI Identifier:
- 873638
- Patent Number(s):
- 6209077
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- purpose; programmable; accelerator; board; acceleration; method; comprising; logic; devices; plurality; memory; blocks; bus; interface; communicating; data; external; dynamic; programming; capabilities; providing; device; executed; method comprising; programmable logic; dynamic programming; memory block; communicating data; accelerator board; logic devices; /712/345/708/710/711/
Citation Formats
Robertson, Perry J, and Witzke, Edward L. General purpose programmable accelerator board. United States: N. p., 2001.
Web.
Robertson, Perry J, & Witzke, Edward L. General purpose programmable accelerator board. United States.
Robertson, Perry J, and Witzke, Edward L. Mon .
"General purpose programmable accelerator board". United States. https://www.osti.gov/servlets/purl/873638.
@article{osti_873638,
title = {General purpose programmable accelerator board},
author = {Robertson, Perry J and Witzke, Edward L},
abstractNote = {A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2001},
month = {1}
}
Works referenced in this record:
Accelerating Adobe Photoshop with reconfigurable logic
conference, January 1998
- Singh, S.; Slous, R.
- Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)