Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same
An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA)
- DOE Contract Number:
- AC52-07NA27344; B621073
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 10,707,755
- Application Number:
- 16/257,861
- OSTI ID:
- 1735016
- Resource Relation:
- Patent File Date: 01/25/2019
- Country of Publication:
- United States
- Language:
- English
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