Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

Zhang, Xin; Takken, Todd Edward; Wu, Chung-shiang; Senger, Robert Matthew; Haring, Rudolf Adriaan; Ohmacht, Martin

Title: Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

Abstract

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Inventors:: Zhang, Xin; Takken, Todd Edward; Wu, Chung-shiang; Senger, Robert Matthew; Haring, Rudolf Adriaan; Ohmacht, Martin

Issue Date:: 2020-07-07

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE National Nuclear Security Administration (NNSA)

OSTI Identifier:: 1735016

Patent Number(s):: 10707755

Application Number:: 16/257,861

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

H - ELECTRICITY H02 - GENERATION H02M - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS

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H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K19/1737 - {using multiplexers
H03K19/01855 - {synchronous, i.e. using clock signals}

H - ELECTRICITY H02 - GENERATION H02M - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS
H02M3/157 - with digital control

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L27/115 - Electrically programmable read-only memories

H - ELECTRICITY H02 - GENERATION H02M - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS
H02M1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L27/11206 - {Programmable ROM [PROM], e.g. memory cells comprising a transistor and a fuse or an antifuse}

H - ELECTRICITY H02 - GENERATION H02M - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS
H02M3/33538 - {of the forward type

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DOE Contract Number:: AC52-07NA27344; B621073

Resource Type:: Patent

Resource Relation:: Patent File Date: 01/25/2019

Country of Publication:: United States

Language:: English

Citation Formats


                    Zhang, Xin, Takken, Todd Edward, Wu, Chung-shiang, Senger, Robert Matthew, Haring, Rudolf Adriaan, and Ohmacht, Martin. Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same.  United States: N. p., 2020. 
        Web.

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                    Zhang, Xin, Takken, Todd Edward, Wu, Chung-shiang, Senger, Robert Matthew, Haring, Rudolf Adriaan, & Ohmacht, Martin. Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same.  United States.

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                    Zhang, Xin, Takken, Todd Edward, Wu, Chung-shiang, Senger, Robert Matthew, Haring, Rudolf Adriaan, and Ohmacht, Martin. Tue .  
        "Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same".  United States.  https://www.osti.gov/servlets/purl/1735016.

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@article{osti_1735016,

  title        = {Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same},

  author       = {Zhang, Xin and Takken, Todd Edward and Wu, Chung-shiang and Senger, Robert Matthew and Haring, Rudolf Adriaan and Ohmacht, Martin},

  abstractNote = {An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {7}

}

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Works referenced in this record:

Dynamically programmable gate array with multiple contexts
patent, April 1998

Dehon, Andre; Knight, Jr., Thomas F.; Tau, Edward
US Patent Document 5,742,180
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5742180

Method to control striations in a lamp powered by an electronic ballast
patent, April 2016

Mays, II, Stephen D.; Dernovsek, John J.; Dyer, Brandon
US Patent Document 9,307,623
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9307623

Constant current controller with selectable gain
patent, November 2013

Melanson, John L.; Singh, Rahul; Maru, Siddharth
US Patent Document 8,593,075
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8593075

Switched-capacitor power supply system and method
patent, March 2007

Azrai, Firas; Yates, Michael; Nelms, David Martin
US Patent Document 7,190,210
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7190210

Basic cell architecture for mask programmable gate array with 3 or more size transistors
patent, February 1994

El Gamal, Abbas
US Patent Document 5,289,021
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5289021

Switching power converter method
patent, February 2006

Kernahan, Kent; Thomas, John Carl
US Patent Document 7,002,328
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7002328

Control parameter adjustment in a discontinuous power mode
patent, April 2014

Sreenivas, Venkat; Carroll, Robert T.
US Patent Document 8,692,535
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8692535

Multiple inverter system with single controller and related operating method
patent, October 2007

Stancu, Constantin C.; Selogie, Mark L.
US Patent Document 7,277,304
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7277304

Rewriteable electronic fuses
patent, June 2008

Diorio, Christopher J.; Bernard, Frédéric J.; Humes, Todd E.
US Patent Document 7,388,420
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7388420

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Title: Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

Abstract

Citation Formats

Dynamically programmable gate array with multiple contexts patent, April 1998

Method to control striations in a lamp powered by an electronic ballast patent, April 2016

Constant current controller with selectable gain patent, November 2013

Switched-capacitor power supply system and method patent, March 2007

Basic cell architecture for mask programmable gate array with 3 or more size transistors patent, February 1994

Switching power converter method patent, February 2006

Control parameter adjustment in a discontinuous power mode patent, April 2014

Multiple inverter system with single controller and related operating method patent, October 2007

Rewriteable electronic fuses patent, June 2008

Dynamically programmable gate array with multiple contexts
patent, April 1998

Method to control striations in a lamp powered by an electronic ballast
patent, April 2016

Constant current controller with selectable gain
patent, November 2013

Switched-capacitor power supply system and method
patent, March 2007

Basic cell architecture for mask programmable gate array with 3 or more size transistors
patent, February 1994

Switching power converter method
patent, February 2006

Control parameter adjustment in a discontinuous power mode
patent, April 2014

Multiple inverter system with single controller and related operating method
patent, October 2007

Rewriteable electronic fuses
patent, June 2008