Silicon on insulator with active buried regions

McCarthy, Anthony M

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Title: Silicon on insulator with active buried regions

Abstract

A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.

Inventors:

McCarthy, Anthony M ^[1]

Menlo Park, CA

Issue Date:: Mon Jan 01 00:00:00 EST 1996

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

OSTI Identifier:: 870276

Patent Number(s):: 5488012

Assignee:: Regents of University of California (Oakland, CA)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L21/2007 - {Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
H01L21/30608 - {Anisotropic liquid etching
H01L21/74 - Making of {localized} buried regions, e.g. buried collector layers, internal connections {substrate contacts}
H01L21/743 - {Making of internal connections, substrate contacts}
H01L21/76251 - {using bonding techniques}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/012 - Bonding, e.g. electrostatic for strain gauges
Y10S148/15 - Silicon on sapphire SOS
Y10S438/97 - Specified etch stop material

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DOE Contract Number:: W-7405-ENG-48

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: silicon; insulator; active; buried; regions; method; forming; patterned; components; collectors; sources; drains; silicon-on-insulator; soi; devices; carried; epitaxially; growing; suitable; sequence; single; multiple; etch; stop; layers; layer; substrate; masking; desired; pattern; exposed; introducing; dopant; activating; form; doped; bonding; removing; additionally; involves; electrical; contact; etch stop; top layer; silicon layer; electrical contact; silicon substrate; involves forming; desired pattern; stop layer; method additionally; insulator substrate; doped regions; forming electrical; patterned buried; epitaxially growing; introducing dopant; suitable sequence; forming patterned; buried regions; buried components; active buried; /438/148/

Citation Formats


                    McCarthy, Anthony M. Silicon on insulator with active buried regions.  United States: N. p., 1996. 
        Web.

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                    McCarthy, Anthony M. Silicon on insulator with active buried regions.  United States.

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                    McCarthy, Anthony M. Mon .  
        "Silicon on insulator with active buried regions".  United States.  https://www.osti.gov/servlets/purl/870276.

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@article{osti_870276,

  title        = {Silicon on insulator with active buried regions},

  author       = {McCarthy, Anthony M},

  abstractNote = {A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Mon Jan 01 00:00:00 EST 1996},

  month        = {Mon Jan 01 00:00:00 EST 1996}

}

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Works referenced in this record:

A technology for high-performance single-crystal silicon-on-insulator transistors
journal, April 1987

Spangler, L. J.; Wise, K. D.
IEEE Electron Device Letters, Vol. 8, Issue 4
https://doi.org/10.1109/EDL.1987.26579

Low-temperature fabrication of p/sup +/-n diodes with 300-AA junction depth
journal, July 1992

Weiner, K. H.; Carey, P. G.; McCarthy, A. M.
IEEE Electron Device Letters, Vol. 13, Issue 7
https://doi.org/10.1109/55.192758

Laser crystallization of Si films on glass
journal, March 1982

Lemons, R. A.; Bosch, M. A.; Dayem, A. H.
Applied Physics Letters, Vol. 40, Issue 6
https://doi.org/10.1063/1.93137

Nanosecond Thermal Processing for Ultra-High-Speed Device Technology
journal, January 1989

Sigmon, Thomas W.; McCarthy, Anthony M.; Weiner, CA Kurt H.
MRS Proceedings, Vol. 158
https://doi.org/10.1557/PROC-158-241

Silicon-on-insulator (SOI) by bonding and ETCH-back
conference, January 1985

Lasky, J. B.; Stiffler, S. R.; White, F. R.
1985 International Electron Devices Meeting
https://doi.org/10.1109/IEDM.1985.191067

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Similar Records

Title: Silicon on insulator with active buried regions

Abstract

Citation Formats

A technology for high-performance single-crystal silicon-on-insulator transistors journal, April 1987

Low-temperature fabrication of p/sup +/-n diodes with 300-AA junction depth journal, July 1992

Laser crystallization of Si films on glass journal, March 1982

Nanosecond Thermal Processing for Ultra-High-Speed Device Technology journal, January 1989

Silicon-on-insulator (SOI) by bonding and ETCH-back conference, January 1985

A technology for high-performance single-crystal silicon-on-insulator transistors
journal, April 1987

Low-temperature fabrication of p/sup +/-n diodes with 300-AA junction depth
journal, July 1992

Laser crystallization of Si films on glass
journal, March 1982

Nanosecond Thermal Processing for Ultra-High-Speed Device Technology
journal, January 1989

Silicon-on-insulator (SOI) by bonding and ETCH-back
conference, January 1985