Method and apparatus of integrating memory stacks
Abstract
A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Sunnyvale, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1987224
- Patent Number(s):
- 11604754
- Application Number:
- 15/605,291
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- AC52-07NA27344; B608045
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 05/25/2017
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Yudanov, Dmitri, and Ignatowski, Michael. Method and apparatus of integrating memory stacks. United States: N. p., 2023.
Web.
Yudanov, Dmitri, & Ignatowski, Michael. Method and apparatus of integrating memory stacks. United States.
Yudanov, Dmitri, and Ignatowski, Michael. Tue .
"Method and apparatus of integrating memory stacks". United States. https://www.osti.gov/servlets/purl/1987224.
@article{osti_1987224,
title = {Method and apparatus of integrating memory stacks},
author = {Yudanov, Dmitri and Ignatowski, Michael},
abstractNote = {A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 14 00:00:00 EDT 2023},
month = {Tue Mar 14 00:00:00 EDT 2023}
}
Works referenced in this record:
Serial Memory Interface
patent-application, December 2007
- Norman, Robert
- US Patent Application 11/449105; 20070286009
Die-Stacked Device With Partitioned Multi-Hop Network
patent-application, June 2014
- Thottethodi, Mithuna; Loh, Gabriel
- US Patent Application 13/726142; 20140177626
System, method, and computer program product for improving memory systems
patent, August 2016
- Smith, Michael
- US Patent Document 9,432,298
Multiple Layers of Memory Implemented as Different Memory Technology
patent-application, August 2010
- Norman, Robert
- US Patent Application 12/653853; 20100195363
Multi-Die Dram Banks Arrangement and Wiring
patent-application, December 2015
- Vogelsang, Thomas
- US Patent Application 14/807786; 20150348613
On Chip Redundancy Repair for Memory Devices
patent-application, January 2014
- Kobla, Darshan; Zimmerman, David J.; Natarajan, Vimal K.
- US Patent Application 13/976409; 20140013185