Method and apparatus for selective and power-aware memory error protection and memory management
A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B599858
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 10,141,955
- Application Number:
- 14/684,368
- OSTI ID:
- 1495044
- Resource Relation:
- Patent File Date: 2015 Apr 11
- Country of Publication:
- United States
- Language:
- English
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