Method and apparatus for back end gather/scatter memory coalescing

Cain, Harold W.; Lakshminarayana, Nagesh Bangalore; Ernst, Daniel Jonathan; Mehta, Sanyam

Advanced Search OptionsAdvanced Search queries use a traditional Term Search. For more info, see our FAQ.

All Fields:

Patent Title:

Abstract:

Assignee:

Inventor(s):

Patent Number:

Patent Classification (CPC):

All Classifications
A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
A43 - footwear
A44 - haberdashery
A45 - hand or travelling articles
A46 - brushware
A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
B05 - spraying or atomising in general
B06 - generating or transmitting mechanical vibrations in general
B07 - separating solids from solids
B08 - cleaning
B09 - disposal of solid waste
B21 - mechanical metal-working without essentially removing material
B22 - casting
B23 - machine tools
B24 - grinding
B25 - hand tools
B26 - hand cutting tools
B27 - working or preserving wood or similar material
B28 - working cement, clay, or stone
B29 - working of plastics
B30 - presses
B31 - making articles of paper, cardboard or material worked in a manner analogous to paper
B32 - layered products
B33 - additive manufacturing technology
B41 - printing
B42 - bookbinding
B43 - writing or drawing implements
B44 - decorative arts
B60 - vehicles in general
B61 - railways
B62 - land vehicles for travelling otherwise than on rails
B63 - ships or other waterborne vessels
B64 - aircraft
B65 - conveying
B66 - hoisting
B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
B81 - microstructural technology
B82 - nanotechnology
B99 - subject matter not otherwise provided for in this section
C - chemistry
C01 - inorganic chemistry
C02 - treatment of water, waste water, sewage, or sludge
C03 - glass
C04 - cements
C05 - fertilisers
C06 - explosives
C07 - organic chemistry
C08 - organic macromolecular compounds
C09 - dyes
C10 - petroleum, gas or coke industries
C11 - animal or vegetable oils, fats, fatty substances or waxes
C12 - biochemistry
C13 - sugar industry
C14 - skins
C21 - metallurgy of iron
C22 - metallurgy
C23 - coating metallic material
C25 - electrolytic or electrophoretic processes
C30 - crystal growth
C40 - combinatorial technology
C99 - subject matter not otherwise provided for in this section
D - textiles
D01 - natural or man-made threads or fibres
D02 - yarns
D03 - weaving
D04 - braiding
D05 - sewing
D06 - treatment of textiles or the like
D07 - ropes
D10 - indexing scheme associated with sublasses of section d, relating to textiles
D21 - paper-making
D99 - subject matter not otherwise provided for in this section
E - fixed constructions
E01 - construction of roads, railways, or bridges
E02 - hydraulic engineering
E03 - water supply
E04 - building
E05 - locks
E06 - doors, windows, shutters, or roller blinds in general
E21 - earth drilling
E99 - subject matter not otherwise provided for in this section
F - mechanical engineering
F01 - machines or engines in general
F02 - combustion engines
F03 - machines or engines for liquids
F04 - positive - displacement machines for liquids
F05 - indexing schemes relating to engines or pumps in various subclasses of classes f01-f04
F15 - fluid-pressure actuators
F16 - engineering elements and units
F17 - storing or distributing gases or liquids
F21 - lighting
F22 - steam generation
F23 - combustion apparatus
F24 - heating
F25 - refrigeration or cooling
F26 - drying
F27 - furnaces
F28 - heat exchange in general
F41 - weapons
F42 - ammunition
F99 - subject matter not otherwise provided for in this section
G - physics
G01 - measuring
G02 - optics
G03 - photography
G04 - horology
G05 - controlling
G06 - computing
G07 - checking-devices
G08 - signalling
G09 - education
G10 - musical instruments
G11 - information storage
G12 - instrument details
G16 - information and communication technology [ict] specially adapted for specific application fields
G21 - nuclear physics
G99 - subject matter not otherwise provided for in this section
H - electricity
H01 - basic electric elements
H02 - generation
H03 - basic electronic circuitry
H04 - electric communication technique
H05 - electric techniques not otherwise provided for
H99 - subject matter not otherwise provided for in this section
Y - new / cross sectional technologies
Y02 - technologies or applications for mitigation or adaptation against climate change
Y04 - information or communication technologies having an impact on other technology areas
Y10 - technical subjects covered by former uspc

More Options ...

Title: Method and apparatus for back end gather/scatter memory coalescing

Abstract

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

Inventors:: Cain, III, Harold W.; Lakshminarayana, Nagesh Bangalore; Ernst, Daniel Jonathan; Mehta, Sanyam

Issue Date:: Tue Jan 31 00:00:00 EST 2023

Research Org.:: Marvell Asia PTE, Ltd. (Singapore); Cray Inc., Seattle, WA (United States); Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1987088

Patent Number(s):: 11567771

Application Number:: 16/944,146

Assignee:: Marvell Asia Pte Ltd (Singapore, SG); Cray Inc. (Seattle, WA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/30043 - {LOAD or STORE instructions
G06F9/30047 - {Prefetch instructions
G06F9/30145 - {Instruction analysis, e.g. decoding, instruction word fields}
G06F9/30181 - {Instruction operation extension or modification}
G06F9/3834 - {Maintaining memory consistency
G06F9/546 - {Message passing systems or structures, e.g. queues}

Show less

DOE Contract Number:: AC52-07NA27344; B620872

Resource Type:: Patent

Resource Relation:: Patent File Date: 07/30/2020

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Cain, III, Harold W., Lakshminarayana, Nagesh Bangalore, Ernst, Daniel Jonathan, and Mehta, Sanyam. Method and apparatus for back end gather/scatter memory coalescing.  United States: N. p., 2023. 
        Web.

Copy to clipboard


                    Cain, III, Harold W., Lakshminarayana, Nagesh Bangalore, Ernst, Daniel Jonathan, & Mehta, Sanyam. Method and apparatus for back end gather/scatter memory coalescing.  United States.

Copy to clipboard


                    Cain, III, Harold W., Lakshminarayana, Nagesh Bangalore, Ernst, Daniel Jonathan, and Mehta, Sanyam. Tue .  
        "Method and apparatus for back end gather/scatter memory coalescing".  United States.  https://www.osti.gov/servlets/purl/1987088.

Copy to clipboard


                    
@article{osti_1987088,

  title        = {Method and apparatus for back end gather/scatter memory coalescing},

  author       = {Cain, III, Harold W. and Lakshminarayana, Nagesh Bangalore and Ernst, Daniel Jonathan and Mehta, Sanyam},

  abstractNote = {A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Jan 31 00:00:00 EST 2023},

  month        = {Tue Jan 31 00:00:00 EST 2023}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

System and Method for Store Fusion
patent-application, May 2019

King, John M.
US Patent Application 15/822515; 20190163475
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20190163475

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017

Chen, Chia-yu; Gopalakrishnan, Kailash; Oh, Jinwook
US Patent Application 14/932672; 20170123795
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170123795

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System
patent-application, November 2017

Guthrie, Guy L.; Shen, Hugh; Williams, Derek E.
US Patent Application 15/141013; 20170315922
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170315922

Solid State Drive (SSD) Memory Cache Occupancy Prediction
patent-application, May 2016

Ghosh, Mrinmoy
US Patent Application 14/813070; 20160147446
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160147446

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017

Chen, Chia-Yu; Gopalakrishnan, Kailash; Oh, Jinwook
US Patent Application 14/932629; 20170123794
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170123794

Method and system for front-end gathering of store instructions within a data-processing system
patent, August 1999

Arimilli, Ravi Kumar; Dodson, John Steven; Lewis, Jerry Don
US Patent Document 5,940,611
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5940611

Technique to Combine Instructions
patent-application, February 2007

Valentine, Robert; Anati, Ittai; Sperber, Zeev
US Patent Application 11/200777; 20070038844
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070038844

Coalescing memory transactions
patent, September 2015

Busaba, Fadi Y.; Gschwind, Michael K.; Michael, Maged M.
US Patent Document 9,146,774
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9146774

Apparatus and Method for Processing Structure of Arrays (SoA) and Array of Structures (AoS) Data
patent-application, March 2020

Hughes, Christopher J.; Toll, Bret; Heinecke, Alexander
US Patent Application 16/140294; 20200097298
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20200097298

Code optimization to enable and disable coalescing of memory transactions
patent, May 2016

Busaba, Fadi Y.; Gschwind, Michael K.; Michael, Maged M.
US Patent Document 9,348,523
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9348523

Code optimization to enable and disable coalescing of memory transactions
patent, July 2016

Busaba, Fadi Y.; Gschwind, Michael K.; Michael, Maged M.
US Patent Document 9,383,930
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9383930

Software indications and hints for coalescing memory transactions
patent, May 2016

Busaba, Fadi Y.; Gschwind, Michael K.; Salapura, Valentina
US Patent Document 9,348,522
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9348522

Apparatus and Method for Efficient Gather and Scatter Operations
patent-application, April 2014

Grochowski, Edward T.; Bradford, Dennis R.; Chrysos, George Z.
US Patent Application 13/631071; 20140095831
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140095831

Unordered load/store queue
patent, May 2013

Burger, Douglas C.; Keckler, Stephen W.; McDonald, Robert Gregory
US Patent Document 8,447,911
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8447911

Scatter Using Index Array and Finite State Machine
patent-application, March 2015

Sperber, Zeev; Valentine, Robert; Raikin, Shlomo
US Patent Application 13/977727; 20150074373
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150074373

Instruction Context Switching
patent-application, December 2016

Yudanov, Dmitri; Blagodurov, Sergey; Basu, Arkaprava
US Patent Application 14/746601; 20160371082
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160371082

Processing of Temporary-Register-Using Instruction
patent-application, February 2020

Shen, Xiaoyang; Martin, Damien Robin; Airaud, Cedric Denis Robert
US Patent Application 16/524667; 20200065109
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20200065109

Operation Cache Compression
patent-application, March 2021

Schinzler, Michael Brian; Filippo, Michael
US Patent Application 16/552001; 20210064533
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20210064533

Dynamic predictor for coalescing memory transactions
patent, April 2017

Busaba, Fadi Y.; Cain, III, Harold W.; Gschwind, Michael K.
US Patent Document 9,619,383
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9619383

Methods and Apparatus for Combining a Plurality of Memory Access Transactions
patent-application, December 2002

Tremblay, Marc; Keskar, Shrinath
US Patent Application 09/325625; 20020184460
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020184460

Apparatus and Method for Tile Gather and Tile Scatter
patent-application, March 2020

Hughes, Christopher J.; Toll, Bret; Heinecke, Alexander
US Patent Application 16/140196; 20200097291
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20200097291

Gather Using Index Array and Finite State Machine
patent-application, April 2016

Sperber, Zeev; Valentine, Robert; Patkin, Guy
US Patent Application 14/881111; 20160103785
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160103785

Method and system for front-end and back-end gathering of store instructions within a data-processing system
patent, September 1999

Arimilli, Ravi Kumar; Dodson, John Steven; Lewis, Jerry Don
US Patent Document 5,956,503
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5956503

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
patent, September 1997

Akkary, Haitham; Abramson, Jeffrey M.; Glew, Andrew F.
US Patent Document 5,671,444
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5671444

Dynamic Predictor for Coalescing Memory Transactions
patent-application, June 2015

Busaba, Fadi Y.; Cain, III, Harold W.; Gschwind, Michael Karl
US Patent Application 14/104380; 20150169361
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150169361

Software indications and hints for coalescing memory transactions
patent, June 2016

Busaba, Fadi Y.; Gschwind, Michael K.; Salapura, Valentina
US Patent Document 9,361,031
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9361031

Dynamic Predictor for Coalescing Memory Transactions
patent-application, December 2015

Busaba, Fadi Y.; Cain III, Harold W.; Gschwind, Michael Karl
US Patent Application 14/845403; 20150378907
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150378907

Coalescing Adjacent Gather/Scatter Operations
patent-application, June 2014

Forsyth, Andrew T.; Hickmann, Brian J.; Hall, Jonathan C.
US Patent Application 13/997784; 20140181464
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140181464

Coalescing memory transactions
patent, August 2016

Busaba, Fadi Y.; Gschwind, Michael K.; Michael, Maged M.
US Patent Document 9,430,276
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9430276

Circuitry and Method
patent-application, January 2021

Raja, Abhishek; Filippo, Michael; Sanjeliwala, Huzefa Moiz
US Patent Application 16/521748; 20210026627
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20210026627

Gather Using Index Array and Finite State Machine
patent-application, December 2013

Sperber, Zeev; Valentine, Robert; Patkin, Guv
US Patent Application 13/487184; 20130326160
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130326160

Fused Adjacent Memory Stores
patent-application, April 2018

Winkel, Sebastian; Collins, Jamison D.; Sondag, Tyler
US Patent Application 15/281957; 20180095761
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20180095761

Dynamic predictor for coalescing memory transactions
patent, October 2015

Busaba, Fadi Y.; Cain, III, Harold W.; Gschwind, Michael K.
US Patent Document 9,158,573
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9158573

Method and apparatus for processing storage instructions
patent, January 2021

Lichtenau, Cedric; Altevogt, Peter; Pflueger, Thomas
US Patent Document 10,901,745
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/10901745

Multi-level store merging in a cache and memory hierarchy
patent, March 2016

Kruckemyer, David A.; Favor, John G.; Ashcraft, Matthew
US Patent Document 9,280,479
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9280479

Aggregate Scatter Instructions
patent-application, June 2017

Jha, Ashish; Ould-Ahmed-Vall, Elmoustapha; Valentine, Robert
US Patent Application 14/979047; 20170177543
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170177543

Aggressive Store Merging in a Processor that Supports Checkpointing
patent-application, December 2009

Caprioli, Paul; Karlsson, Martin; Levinsky, Gideon N.
US Patent Application 12/128332; 20090300338
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090300338

Method and apparatus for improving cache efficiency
patent, January 2015

Jamil, Sujat; O'Bleness, R. Frank; Robideau, Russell J.
US Patent Document 8,943,273
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8943273

Gathering and Scattering Multiple Data Elements
patent-application, November 2014

Hughes, Christopher J.; Chen, Yen-Kuang (Y. K.); Bomb, Mayank
US Patent Application 13/898189; 20140344553
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140344553

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System
patent-application, November 2017

Guthrie, Guy L.; Shen, Hugh; Williams, Derek E.
US Patent Application 15/141030; 20170315919
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170315919

Similar Records in DOE Patents and OSTI.GOV collections:

Method and apparatus for front end gather/scatter memory coalescing

Patent Cain, III, Harold Wade; Sugumar, Rabin Andrew; Lakshminarayana, Nagesh Bangalore; ...

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality ofmore » « less
Full Text Available
Distributed gather/scatter operations across a network of memory nodes

Patent Farmahini-Farahani, Amin; Roberts, David A.

Devices, methods, and systems for distributed gather and scatter operations in a network of memory nodes. A responding memory node includes a memory; a communications interface having circuitry configured to communicate with at least one other memory node; and a controller. The controller includes circuitry configured to receive a request message from a requesting node via the communications interface. The request message indicates a gather or scatter operation, and instructs the responding node to retrieve data elements from a source memory data structure and store the data elements to a destination memory data structure. The controller further includes circuitry configuredmore » « less
Full Text Available
Method and apparatus of performing a memory operation in a hierarchical memory assembly

Patent Yudanov, Dmitri

A method and apparatus of performing a memory operation includes receiving a memory operation request at a first memory controller that is in communication with a second memory controller. The first memory controller forwards the memory operation request to the second memory controller. Upon receipt of the memory operation request, the second memory controller provides first information or second information depending on a condition of a pseudo-bank of the second memory controller and a type of the memory operation request.
Full Text Available
Method and apparatus for selective and power-aware memory error protection and memory management

Patent Andrade Costa, Carlos H.; Cher, Chen-Yong; Park, Yoonho; ...

A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot bemore » « less
Full Text Available
Method and apparatus for back-extracting metal chelates

Patent Wai, Chien M [Moscow, IA]; Smart, Neil G [Moscow, IA]; Lin, Yuehe [Moscow, IA]

A method of extracting metal and metalloid species from a solid or liquid substrate using a supercritical fluid solvent containing one or more chelating agents followed by back-extracting the metal and metalloid species from the metal and metalloid chelates formed thereby. The back-extraction acidic solution is performed utilizing an acidic solution. Upon sufficient exposure of the metal and metalloid chelates to the acidic solution, the metal and metalloid species are released from the chelates into the acid solution, while the chelating agent remains in the supercritical fluid solvent. The chelating agent is thereby regenerated and the metal and metalloid speciesmore » recovered. « less
Full Text Available

Similar Records

Title: Method and apparatus for back end gather/scatter memory coalescing

Abstract

Citation Formats

System and Method for Store Fusion patent-application, May 2019

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits patent-application, May 2017

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System patent-application, November 2017

Solid State Drive (SSD) Memory Cache Occupancy Prediction patent-application, May 2016

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits patent-application, May 2017

Method and system for front-end gathering of store instructions within a data-processing system patent, August 1999

Technique to Combine Instructions patent-application, February 2007

Coalescing memory transactions patent, September 2015

Apparatus and Method for Processing Structure of Arrays (SoA) and Array of Structures (AoS) Data patent-application, March 2020

Code optimization to enable and disable coalescing of memory transactions patent, May 2016

Code optimization to enable and disable coalescing of memory transactions patent, July 2016

Software indications and hints for coalescing memory transactions patent, May 2016

Apparatus and Method for Efficient Gather and Scatter Operations patent-application, April 2014

Unordered load/store queue patent, May 2013

Scatter Using Index Array and Finite State Machine patent-application, March 2015

Instruction Context Switching patent-application, December 2016

Processing of Temporary-Register-Using Instruction patent-application, February 2020

Operation Cache Compression patent-application, March 2021

Dynamic predictor for coalescing memory transactions patent, April 2017

Methods and Apparatus for Combining a Plurality of Memory Access Transactions patent-application, December 2002

Apparatus and Method for Tile Gather and Tile Scatter patent-application, March 2020

Gather Using Index Array and Finite State Machine patent-application, April 2016

Method and system for front-end and back-end gathering of store instructions within a data-processing system patent, September 1999

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers patent, September 1997

Dynamic Predictor for Coalescing Memory Transactions patent-application, June 2015

Software indications and hints for coalescing memory transactions patent, June 2016

Dynamic Predictor for Coalescing Memory Transactions patent-application, December 2015

Coalescing Adjacent Gather/Scatter Operations patent-application, June 2014

Coalescing memory transactions patent, August 2016

Circuitry and Method patent-application, January 2021

Gather Using Index Array and Finite State Machine patent-application, December 2013

Fused Adjacent Memory Stores patent-application, April 2018

Dynamic predictor for coalescing memory transactions patent, October 2015

Method and apparatus for processing storage instructions patent, January 2021

Multi-level store merging in a cache and memory hierarchy patent, March 2016

Aggregate Scatter Instructions patent-application, June 2017

Aggressive Store Merging in a Processor that Supports Checkpointing patent-application, December 2009

Method and apparatus for improving cache efficiency patent, January 2015

Gathering and Scattering Multiple Data Elements patent-application, November 2014

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System patent-application, November 2017

System and Method for Store Fusion
patent-application, May 2019

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System
patent-application, November 2017

Solid State Drive (SSD) Memory Cache Occupancy Prediction
patent-application, May 2016

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017

Method and system for front-end gathering of store instructions within a data-processing system
patent, August 1999

Technique to Combine Instructions
patent-application, February 2007

Coalescing memory transactions
patent, September 2015

Apparatus and Method for Processing Structure of Arrays (SoA) and Array of Structures (AoS) Data
patent-application, March 2020

Code optimization to enable and disable coalescing of memory transactions
patent, May 2016

Code optimization to enable and disable coalescing of memory transactions
patent, July 2016

Software indications and hints for coalescing memory transactions
patent, May 2016

Apparatus and Method for Efficient Gather and Scatter Operations
patent-application, April 2014

Unordered load/store queue
patent, May 2013

Scatter Using Index Array and Finite State Machine
patent-application, March 2015

Instruction Context Switching
patent-application, December 2016

Processing of Temporary-Register-Using Instruction
patent-application, February 2020

Operation Cache Compression
patent-application, March 2021

Dynamic predictor for coalescing memory transactions
patent, April 2017

Methods and Apparatus for Combining a Plurality of Memory Access Transactions
patent-application, December 2002

Apparatus and Method for Tile Gather and Tile Scatter
patent-application, March 2020

Gather Using Index Array and Finite State Machine
patent-application, April 2016

Method and system for front-end and back-end gathering of store instructions within a data-processing system
patent, September 1999

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
patent, September 1997

Dynamic Predictor for Coalescing Memory Transactions
patent-application, June 2015

Software indications and hints for coalescing memory transactions
patent, June 2016

Dynamic Predictor for Coalescing Memory Transactions
patent-application, December 2015

Coalescing Adjacent Gather/Scatter Operations
patent-application, June 2014

Coalescing memory transactions
patent, August 2016

Circuitry and Method
patent-application, January 2021

Gather Using Index Array and Finite State Machine
patent-application, December 2013

Fused Adjacent Memory Stores
patent-application, April 2018

Dynamic predictor for coalescing memory transactions
patent, October 2015

Method and apparatus for processing storage instructions
patent, January 2021

Multi-level store merging in a cache and memory hierarchy
patent, March 2016

Aggregate Scatter Instructions
patent-application, June 2017

Aggressive Store Merging in a Processor that Supports Checkpointing
patent-application, December 2009

Method and apparatus for improving cache efficiency
patent, January 2015

Gathering and Scattering Multiple Data Elements
patent-application, November 2014

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System
patent-application, November 2017