Method and apparatus for back end gather/scatter memory coalescing

Cain, Harold W.; Lakshminarayana, Nagesh Bangalore; Ernst, Daniel Jonathan; Mehta, Sanyam

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Title: Method and apparatus for back end gather/scatter memory coalescing

Abstract

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

Inventors:: Cain, III, Harold W.; Lakshminarayana, Nagesh Bangalore; Ernst, Daniel Jonathan; Mehta, Sanyam

Issue Date:: 2023-01-31

Research Org.:: Marvell Asia PTE, Ltd. (Singapore); Cray Inc., Seattle, WA (United States); Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1987088

Patent Number(s):: 11567771

Application Number:: 16/944,146

Assignee:: Marvell Asia Pte Ltd (Singapore, SG); Cray Inc. (Seattle, WA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/30043 - {LOAD or STORE instructions
G06F9/30047 - {Prefetch instructions
G06F9/30145 - {Instruction analysis, e.g. decoding, instruction word fields}
G06F9/30181 - {Instruction operation extension or modification}
G06F9/3834 - {Maintaining memory consistency
G06F9/546 - {Message passing systems or structures, e.g. queues}

Show less

DOE Contract Number:: AC52-07NA27344; B620872

Resource Type:: Patent

Resource Relation:: Patent File Date: 07/30/2020

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Cain, III, Harold W., Lakshminarayana, Nagesh Bangalore, Ernst, Daniel Jonathan, and Mehta, Sanyam. Method and apparatus for back end gather/scatter memory coalescing.  United States: N. p., 2023. 
        Web.

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                    Cain, III, Harold W., Lakshminarayana, Nagesh Bangalore, Ernst, Daniel Jonathan, & Mehta, Sanyam. Method and apparatus for back end gather/scatter memory coalescing.  United States.

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                    Cain, III, Harold W., Lakshminarayana, Nagesh Bangalore, Ernst, Daniel Jonathan, and Mehta, Sanyam. Tue .  
        "Method and apparatus for back end gather/scatter memory coalescing".  United States.  https://www.osti.gov/servlets/purl/1987088.

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@article{osti_1987088,

  title        = {Method and apparatus for back end gather/scatter memory coalescing},

  author       = {Cain, III, Harold W. and Lakshminarayana, Nagesh Bangalore and Ernst, Daniel Jonathan and Mehta, Sanyam},

  abstractNote = {A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2023},

  month        = {1}

}

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Similar Records

Title: Method and apparatus for back end gather/scatter memory coalescing

Abstract

Citation Formats

System and Method for Store Fusion patent-application, May 2019

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits patent-application, May 2017

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System patent-application, November 2017

Solid State Drive (SSD) Memory Cache Occupancy Prediction patent-application, May 2016

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits patent-application, May 2017

Method and system for front-end gathering of store instructions within a data-processing system patent, August 1999

Technique to Combine Instructions patent-application, February 2007

Coalescing memory transactions patent, September 2015

Apparatus and Method for Processing Structure of Arrays (SoA) and Array of Structures (AoS) Data patent-application, March 2020

Code optimization to enable and disable coalescing of memory transactions patent, May 2016

Code optimization to enable and disable coalescing of memory transactions patent, July 2016

Software indications and hints for coalescing memory transactions patent, May 2016

Apparatus and Method for Efficient Gather and Scatter Operations patent-application, April 2014

Unordered load/store queue patent, May 2013

Scatter Using Index Array and Finite State Machine patent-application, March 2015

Instruction Context Switching patent-application, December 2016

Processing of Temporary-Register-Using Instruction patent-application, February 2020

Operation Cache Compression patent-application, March 2021

Dynamic predictor for coalescing memory transactions patent, April 2017

Methods and Apparatus for Combining a Plurality of Memory Access Transactions patent-application, December 2002

Apparatus and Method for Tile Gather and Tile Scatter patent-application, March 2020

Gather Using Index Array and Finite State Machine patent-application, April 2016

Method and system for front-end and back-end gathering of store instructions within a data-processing system patent, September 1999

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers patent, September 1997

Dynamic Predictor for Coalescing Memory Transactions patent-application, June 2015

Software indications and hints for coalescing memory transactions patent, June 2016

Dynamic Predictor for Coalescing Memory Transactions patent-application, December 2015

Coalescing Adjacent Gather/Scatter Operations patent-application, June 2014

Coalescing memory transactions patent, August 2016

Circuitry and Method patent-application, January 2021

Gather Using Index Array and Finite State Machine patent-application, December 2013

Fused Adjacent Memory Stores patent-application, April 2018

Dynamic predictor for coalescing memory transactions patent, October 2015

Method and apparatus for processing storage instructions patent, January 2021

Multi-level store merging in a cache and memory hierarchy patent, March 2016

Aggregate Scatter Instructions patent-application, June 2017

Aggressive Store Merging in a Processor that Supports Checkpointing patent-application, December 2009

Method and apparatus for improving cache efficiency patent, January 2015

Gathering and Scattering Multiple Data Elements patent-application, November 2014

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System patent-application, November 2017

System and Method for Store Fusion
patent-application, May 2019

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017

Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System
patent-application, November 2017

Solid State Drive (SSD) Memory Cache Occupancy Prediction
patent-application, May 2016

Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017

Method and system for front-end gathering of store instructions within a data-processing system
patent, August 1999

Technique to Combine Instructions
patent-application, February 2007

Coalescing memory transactions
patent, September 2015

Apparatus and Method for Processing Structure of Arrays (SoA) and Array of Structures (AoS) Data
patent-application, March 2020

Code optimization to enable and disable coalescing of memory transactions
patent, May 2016

Code optimization to enable and disable coalescing of memory transactions
patent, July 2016

Software indications and hints for coalescing memory transactions
patent, May 2016

Apparatus and Method for Efficient Gather and Scatter Operations
patent-application, April 2014

Unordered load/store queue
patent, May 2013

Scatter Using Index Array and Finite State Machine
patent-application, March 2015

Instruction Context Switching
patent-application, December 2016

Processing of Temporary-Register-Using Instruction
patent-application, February 2020

Operation Cache Compression
patent-application, March 2021

Dynamic predictor for coalescing memory transactions
patent, April 2017

Methods and Apparatus for Combining a Plurality of Memory Access Transactions
patent-application, December 2002

Apparatus and Method for Tile Gather and Tile Scatter
patent-application, March 2020

Gather Using Index Array and Finite State Machine
patent-application, April 2016

Method and system for front-end and back-end gathering of store instructions within a data-processing system
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Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
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Dynamic Predictor for Coalescing Memory Transactions
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Software indications and hints for coalescing memory transactions
patent, June 2016

Dynamic Predictor for Coalescing Memory Transactions
patent-application, December 2015

Coalescing Adjacent Gather/Scatter Operations
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Coalescing memory transactions
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Circuitry and Method
patent-application, January 2021

Gather Using Index Array and Finite State Machine
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Fused Adjacent Memory Stores
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Dynamic predictor for coalescing memory transactions
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Method and apparatus for processing storage instructions
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Multi-level store merging in a cache and memory hierarchy
patent, March 2016

Aggregate Scatter Instructions
patent-application, June 2017

Aggressive Store Merging in a Processor that Supports Checkpointing
patent-application, December 2009

Method and apparatus for improving cache efficiency
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Gathering and Scattering Multiple Data Elements
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Implementing Barriers to Efficiently Support Cumulativity in a Weakly-Ordered Memory System
patent-application, November 2017