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Title: Secure true random number generation using 1.5-T transistor flash memory

This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To reduce or eliminate the systematic bias from the array, whitening circuitry is configured to generate a random number comprising random number bits in response to the memory control circuit implementing at least one sequence of memory cycles on the array of the memory cells in the memory. The whitening circuitry is configured to provide the random number bits of the random number based on the variable bit states stored by the array of the memory cells. On average the whitening circuitry is configured to provide approximately half of the random number bits in the first bit state and half of random number bits in a second bit state.
Inventors:
; ;
Issue Date:
OSTI Identifier:
1483257
Assignee:
Arizona Board of Regents on behalf of Arizona State University (Scottsdale, AZ) IDO
Patent Number(s):
10,078,494
Application Number:
15/276,087
Contract Number:
NE0000679
Resource Relation:
Patent File Date: 2016 Sep 26
Research Org:
Arizona Board of Regents on behalf of Arizona State University, Scottsdale, AZ (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING