Testing and operating a multiprocessor chip with processor redundancy

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

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Title: Testing and operating a multiprocessor chip with processor redundancy

Abstract

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Inventors:: Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

Issue Date:: Tue Oct 21 00:00:00 EDT 2014

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1160333

Patent Number(s):: 8868975

Application Number:: 13/196,459

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/202 - {where processing functionality is redundant
G06F11/2242 - {in multi-processor systems, e.g. one processor becoming the test master

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 Aug 02

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy.  United States: N. p., 2014. 
        Web.

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                    Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, & Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy.  United States.

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                    Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Tue .  
        "Testing and operating a multiprocessor chip with processor redundancy".  United States.  https://www.osti.gov/servlets/purl/1160333.

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@article{osti_1160333,

  title        = {Testing and operating a multiprocessor chip with processor redundancy},

  author       = {Bellofatto, Ralph E and Douskey, Steven M and Haring, Rudolf A and McManus, Moyra K and Ohmacht, Martin and Schmunkamp, Dietmar and Sugavanam, Krishnan and Weatherford, Bryan J},

  abstractNote = {A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Oct 21 00:00:00 EDT 2014},

  month        = {Tue Oct 21 00:00:00 EDT 2014}

}

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Similar Records

Title: Testing and operating a multiprocessor chip with processor redundancy

Abstract

Citation Formats

Multiprocessor for providing fault isolation test upon itself patent, January 1980

Reconfigurable computing device patent, January 1990

Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort patent, October 1994

Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor patent, August 1998

Test method of cache memory of multiprocessor system patent, January 2001

Method and apparatus for yield and failure analysis in the manufacturing of semiconductors patent, November 2002

Hybrid bulk/silicon-on-insulator multiprocessors patent, March 2005

Method and apparatus for administering inversion property in a memory tester patent, December 2005

Embedded symmetric multiprocessor system debug patent, March 2006

Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors patent, July 2006

Electronic fuse blow mimic and methods for adjusting electronic fuse blow patent, January 2007

Fault tolerant cell array architecture patent, November 2007

Partial good integrated circuit and method of testing same patent, December 2007

System and method for accessing and operating personal computers remotely patent, June 2010

Structures for wafer level test and burn-in patent-application, November 2001

Method and apparatus for enhancing computer system security patent-application, November 2002

Autonomous fail-over to hot-spare processor using SMI patent-application, August 2005

Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link patent-application, August 2006

Method and system of providing redundancy in a network device patent-application, April 2007

Apparatus and Method for Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device patent-application, December 2007

Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer patent-application, March 2008

Methods and Apparatus for Data Analysis patent-application, April 2008

Method and Apparatus for Repairing a Processor Core During Run Time in a Multi-Processor Data Processing System patent-application, September 2008

Multiple Parallel Pipeline Processor Having Self-Repairing Capability patent-application, February 2009

Self Test Apparatus for Identifying Partially Defective Memory patent-application, August 2009

Online Multiprocessor System Reliability Defect Testing patent-application, September 2009

Semiconductor Chip Repair by Stacking of a Base Semiconductor Chip and a Repair Semiconductor Chip patent-application, January 2010

Reducing Power Requirements of a Multiple Core Processor patent-application, October 2011

On-Chip Non-Volatile Storage of a Test-Time Profile for Efficiency and Performance Control patent-application, November 2011

Multiple word/bit line redundancy for semiconductor memories journal, October 1978

Testing of Vega2, a chip multi-processor with spare processors. conference, October 2007

Multiprocessor for providing fault isolation test upon itself
patent, January 1980

Reconfigurable computing device
patent, January 1990

Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
patent, October 1994

Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
patent, August 1998

Test method of cache memory of multiprocessor system
patent, January 2001

Method and apparatus for yield and failure analysis in the manufacturing of semiconductors
patent, November 2002

Hybrid bulk/silicon-on-insulator multiprocessors
patent, March 2005

Method and apparatus for administering inversion property in a memory tester
patent, December 2005

Embedded symmetric multiprocessor system debug
patent, March 2006

Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors
patent, July 2006

Electronic fuse blow mimic and methods for adjusting electronic fuse blow
patent, January 2007

Fault tolerant cell array architecture
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Partial good integrated circuit and method of testing same
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System and method for accessing and operating personal computers remotely
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Structures for wafer level test and burn-in
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Method and apparatus for enhancing computer system security
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Autonomous fail-over to hot-spare processor using SMI
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Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link
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Method and system of providing redundancy in a network device
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Semiconductor Chip Repair by Stacking of a Base Semiconductor Chip and a Repair Semiconductor Chip
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