Testing and operating a multiprocessor chip with processor redundancy
Abstract
A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1160333
- Patent Number(s):
- 8868975
- Application Number:
- 13/196,459
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2011 Aug 02
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy. United States: N. p., 2014.
Web.
Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, & Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy. United States.
Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Tue .
"Testing and operating a multiprocessor chip with processor redundancy". United States. https://www.osti.gov/servlets/purl/1160333.
@article{osti_1160333,
title = {Testing and operating a multiprocessor chip with processor redundancy},
author = {Bellofatto, Ralph E and Douskey, Steven M and Haring, Rudolf A and McManus, Moyra K and Ohmacht, Martin and Schmunkamp, Dietmar and Sugavanam, Krishnan and Weatherford, Bryan J},
abstractNote = {A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {10}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Multiprocessor for providing fault isolation test upon itself
patent, January 1980
- Underwood, Thomas E.; Holden, III, James J.
- US Patent Document 4,181,940
Reconfigurable computing device
patent, January 1990
- de Corlieu, Patrick; Prevost, Michel; du Chene, Arnaud
- US Patent Document 4,891,810
Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
patent, October 1994
- Weight, Russell H.
- US Patent Document 5,355,471
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
patent, August 1998
- Adams, Robert Dean; Connor, John; Koch, Garrett Stephen
- US Patent Document 5,790,564
Test method of cache memory of multiprocessor system
patent, January 2001
- Ju, Seok-mann; Huh, Hyun
- US Patent Document 6,170,070
Method and apparatus for yield and failure analysis in the manufacturing of semiconductors
patent, November 2002
- Lovelace, Jerome
- US Patent Document 6,477,685
Hybrid bulk/silicon-on-insulator multiprocessors
patent, March 2005
- Masleid, Robert P.; Scott, Gregory S.
- US Patent Document 6,864,524
Method and apparatus for administering inversion property in a memory tester
patent, December 2005
- Krech, Jr., Alan S.; Freeseman, John M.
- US Patent Document 6,973,404
Embedded symmetric multiprocessor system debug
patent, March 2006
- Jahnke, Steven R.
- US Patent Document 7,010,722
Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors
patent, July 2006
- Cook, III, John Howard; Krech, Jr., Alan S.; Jordan, Stephen D.
- US Patent Document 7,076,714
Electronic fuse blow mimic and methods for adjusting electronic fuse blow
patent, January 2007
- Anand, Darren L.; Ouellette, Michael R.; Perry, Troy J.
- US Patent Document 7,170,299
Fault tolerant cell array architecture
patent, November 2007
- Norman, Richard
- US Patent Document 7,299,377
Partial good integrated circuit and method of testing same
patent, December 2007
- Farnsworth, III, Leonard O.; Felske, Michael Z.; Gillis, Pamela S.
- US Patent Document 7,305,600
System and method for accessing and operating personal computers remotely
patent, June 2010
- Anderson, Robin L.; Perholtz, Ronald J.; Hawkins, Dennis
- US Patent Document 7,747,702
Structures for wafer level test and burn-in
patent-application, November 2001
- Barth, John E.; Bertin, Claude L.; Dreibelbis, Jeffrey H.
- US Patent Application 09/803500; 20010046168
Method and apparatus for enhancing computer system security
patent-application, November 2002
- Helbig, SR., Walter A.
- US Patent Application 10/055786; 20020166062
Autonomous fail-over to hot-spare processor using SMI
patent-application, August 2005
- Fox, Thomas James; Kern, Eric R.; Rollins, Michael Scott
- US Patent Application 10/761721; 20050172164
Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link
patent-application, August 2006
- Fields, JR., James Stephen; Floyd, Michael Stephan; Lecocq, Paul Frank
- US Patent Application 11/055847; 20060184706
Method and system of providing redundancy in a network device
patent-application, April 2007
- Khan, Mohiuddin M.; Norton, Stephen
- US Patent Application 11/522122; 20070076594
Apparatus and Method for Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device
patent-application, December 2007
- Datta, Ramyanshu; Fernsler, Matthew E.; Hofstee, Harm P.
- US Patent Application 11/421518; 20070300115
Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer
patent-application, March 2008
- Bernstein, Kerry; Coteus, Paul; Elfadel, Ibrahim M.
- US Patent Application 11/945308; 20080068039
Methods and Apparatus for Data Analysis
patent-application, April 2008
- Miguelanez, Emilio; Scott, Michael J.; LaBonte, Greg
- US Patent Application 11/857654; 20080091977
Method and Apparatus for Repairing a Processor Core During Run Time in a Multi-Processor Data Processing System
patent-application, September 2008
- Duron, Michael Conrad; McLaughlin, Mark David
- US Patent Application 11/689556; 20080235454
Multiple Parallel Pipeline Processor Having Self-Repairing Capability
patent-application, February 2009
- Luick, David Arnold
- US Patent Application 12/254904; 20090044049
Self Test Apparatus for Identifying Partially Defective Memory
patent-application, August 2009
- Huott, William V.; Lund, David J.; Marz, Kenneth H.
- US Patent Application 12/027702; 20090204762
Online Multiprocessor System Reliability Defect Testing
patent-application, September 2009
- Denneau, Monty M.; Iyenger, Vikram; Nigh, Phillip J.
- US Patent Application 12/053642; 20090241124
Semiconductor Chip Repair by Stacking of a Base Semiconductor Chip and a Repair Semiconductor Chip
patent-application, January 2010
- Bose, Pradip; Kursun, Eren; Rivers, Jude A.
- US Patent Application 12/174198; 20100015732
Reducing Power Requirements of a Multiple Core Processor
patent-application, October 2011
- Flachs, Brian K.; Gervais, Gilles; Dhong, Sang H.
- US Patent Application 12/756570; 20110252260
On-Chip Non-Volatile Storage of a Test-Time Profile for Efficiency and Performance Control
patent-application, November 2011
- Kursun, Eren; Emma, Philip G.; Gates, Stephen M.
- US Patent Application 12/771387; 20110271161
Multiple word/bit line redundancy for semiconductor memories
journal, October 1978
- Schuster, S. E.
- IEEE Journal of Solid-State Circuits, Vol. 13, Issue 5
Testing of Vega2, a chip multi-processor with spare processors.
conference, October 2007
- Makar, Samy; Altinis, Tony; Patkar, Niteen
- 2007 IEEE International Test Conference