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Title: Testing and operating a multiprocessor chip with processor redundancy

Abstract

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Inventors:
; ; ; ; ; ; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1160333
Patent Number(s):
8868975
Application Number:
13/196,459
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
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DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2011 Aug 02
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy. United States: N. p., 2014. Web.
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Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, & Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy. United States.
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Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Tue . "Testing and operating a multiprocessor chip with processor redundancy". United States. https://www.osti.gov/servlets/purl/1160333.
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@article{osti_1160333,
title = {Testing and operating a multiprocessor chip with processor redundancy},
author = {Bellofatto, Ralph E and Douskey, Steven M and Haring, Rudolf A and McManus, Moyra K and Ohmacht, Martin and Schmunkamp, Dietmar and Sugavanam, Krishnan and Weatherford, Bryan J},
abstractNote = {A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {10}
}
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Works referenced in this record:

Multiple word/bit line redundancy for semiconductor memories
journal, October 1978

Testing of Vega2, a chip multi-processor with spare processors.
conference, October 2007

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