Testing and operating a multiprocessor chip with processor redundancy
Abstract
A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1160333
- Patent Number(s):
- 8,868,975
- Application Number:
- 13/196,459
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2011 Aug 02
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy. United States: N. p., 2014.
Web.
Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, & Weatherford, Bryan J. Testing and operating a multiprocessor chip with processor redundancy. United States.
Bellofatto, Ralph E, Douskey, Steven M, Haring, Rudolf A, McManus, Moyra K, Ohmacht, Martin, Schmunkamp, Dietmar, Sugavanam, Krishnan, and Weatherford, Bryan J. Tue .
"Testing and operating a multiprocessor chip with processor redundancy". United States. https://www.osti.gov/servlets/purl/1160333.
@article{osti_1160333,
title = {Testing and operating a multiprocessor chip with processor redundancy},
author = {Bellofatto, Ralph E and Douskey, Steven M and Haring, Rudolf A and McManus, Moyra K and Ohmacht, Martin and Schmunkamp, Dietmar and Sugavanam, Krishnan and Weatherford, Bryan J},
abstractNote = {A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {10}
}
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Works referenced in this record:
Method and apparatus for enhancing computer system security
patent-application, November 2002
- Helbig, SR., Walter A.
- US Patent Application 10/055786; 20020166062
Autonomous fail-over to hot-spare processor using SMI
patent-application, August 2005
- Fox, Thomas James; Kern, Eric R.; Rollins, Michael Scott
- US Patent Application 10/761721; 20050172164
Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link
patent-application, August 2006
- Fields, JR., James Stephen; Floyd, Michael Stephan; Lecocq, Paul Frank
- US Patent Application 11/055847; 20060184706
Methods and Apparatus for Data Analysis
patent-application, April 2008
- Miguelanez, Emilio; Scott, Michael J.; LaBonte, Greg
- US Patent Application 11/857654; 20080091977
Method and Apparatus for Repairing a Processor Core During Run Time in a Multi-Processor Data Processing System
patent-application, September 2008
- Duron, Michael Conrad; McLaughlin, Mark David
- US Patent Application 11/689556; 20080235454
Self Test Apparatus for Identifying Partially Defective Memory
patent-application, August 2009
- Huott, William V.; Lund, David J.; Marz, Kenneth H.
- US Patent Application 12/027702; 20090204762
Online Multiprocessor System Reliability Defect Testing
patent-application, September 2009
- Denneau, Monty M.; Iyenger, Vikram; Nigh, Phillip J.
- US Patent Application 12/053642; 20090241124
Reducing Power Requirements of a Multiple Core Processor
patent-application, October 2011
- Flachs, Brian K.; Gervais, Gilles; Dhong, Sang H.
- US Patent Application 12/756570; 20110252260
Multiple word/bit line redundancy for semiconductor memories
journal, October 1978
- Schuster, S. E.
- IEEE Journal of Solid-State Circuits, Vol. 13, Issue 5
Testing of Vega2, a chip multi-processor with spare processors.
conference, October 2007
- Makar, Samy; Altinis, Tony; Patkar, Niteen
- 2007 IEEE International Test Conference