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Title: Filtering micro-operations for a micro-operation cache in a processor

Abstract

A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

Inventors:
; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
2222120
Patent Number(s):
11726783
Application Number:
16/856,832
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 04/23/2020
Country of Publication:
United States
Language:
English

Citation Formats

Scrbak, Marko, Islam, Mahzabeen, Kalamatianos, John, and Kotra, Jagadish B. Filtering micro-operations for a micro-operation cache in a processor. United States: N. p., 2023. Web.
Scrbak, Marko, Islam, Mahzabeen, Kalamatianos, John, & Kotra, Jagadish B. Filtering micro-operations for a micro-operation cache in a processor. United States.
Scrbak, Marko, Islam, Mahzabeen, Kalamatianos, John, and Kotra, Jagadish B. Tue . "Filtering micro-operations for a micro-operation cache in a processor". United States. https://www.osti.gov/servlets/purl/2222120.
@article{osti_2222120,
title = {Filtering micro-operations for a micro-operation cache in a processor},
author = {Scrbak, Marko and Islam, Mahzabeen and Kalamatianos, John and Kotra, Jagadish B.},
abstractNote = {A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {8}
}

Works referenced in this record:

Multiperspective reuse prediction
conference, October 2017


Sampling Dead Block Prediction for Last-Level Caches
conference, December 2010


Trace Cache Filtering
patent-application, July 2002


Selective Bypassing of Allocation in a Cache
patent-application, October 2017


Performance Optimization Based on Data Accesses During Critical Sections
patent-application, October 2011


Micro-operation cache
conference, January 2001

  • Solomon, Baruch; Mendelson, Avi; Orenstein, Doron
  • Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01
  • https://doi.org/10.1145/383082.383085

Dead-block prediction & dead-block correlating prefetchers
conference, January 2001


Power Reduction for Processor Front-End by Caching Decoded Instructions
patent-application, January 2003