Hardware packet pacing using a DMA in a parallel computer

Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

Title: Hardware packet pacing using a DMA in a parallel computer

Abstract

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

Inventors:: Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

Issue Date:: 2013-08-13

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1092967

Patent Number(s):: 8509255

Application Number:: 11/768,682

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F13/128 - {for dedicated transfers to a network

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DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Chen, Dong, Heidelberger, Phillip, and Vranas, Pavlos. Hardware packet pacing using a DMA in a parallel computer.  United States: N. p., 2013. 
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                    Chen, Dong, Heidelberger, Phillip, & Vranas, Pavlos. Hardware packet pacing using a DMA in a parallel computer.  United States.

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                    Chen, Dong, Heidelberger, Phillip, and Vranas, Pavlos. Tue .  
        "Hardware packet pacing using a DMA in a parallel computer".  United States.  https://www.osti.gov/servlets/purl/1092967.

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@article{osti_1092967,

  title        = {Hardware packet pacing using a DMA in a parallel computer},

  author       = {Chen, Dong and Heidelberger, Phillip and Vranas, Pavlos},

  abstractNote = {Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2013},

  month        = {8}

}

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Works referenced in this record:

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Dubois, M.; Scheurich, C.; Briggs, F. A.
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Almási, George; Heidelberger, Philip; Archer, Charles J.
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Intel 870: a building block for cost-effective, scalable servers
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Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
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Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
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Pande, P. P.; Grecu, C.; Jones, M.
IEEE Transactions on Computers, Vol. 54, Issue 8
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Title: Hardware packet pacing using a DMA in a parallel computer

Abstract

Citation Formats

Synchronization, coherence, and event ordering in multiprocessors journal, February 1988

Optimization of MPI collective communication on BlueGene/L systems conference, January 2005

Intel 870: a building block for cost-effective, scalable servers journal, March 2002

Blue Gene/L advanced diagnostics environment journal, March 2005

Directory-based cache coherence in large-scale multiprocessors journal, June 1990

Performance evaluation of adaptive MPI conference, January 2006

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal, August 2005

Overview of the Blue Gene/L system architecture journal, March 2005

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Blue Gene/L advanced diagnostics environment
journal, March 2005

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Performance evaluation of adaptive MPI
conference, January 2006

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005

Overview of the Blue Gene/L system architecture
journal, March 2005