Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

Triggering Klystrons

Technical Report ·
DOI:https://doi.org/10.2172/992929· OSTI ID:992929

To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

Research Organization:
SLAC National Accelerator Laboratory (SLAC)
Sponsoring Organization:
US DOE Office of Science (DOE SC)
DOE Contract Number:
AC02-76SF00515
OSTI ID:
992929
Report Number(s):
SLAC-TN-10-019
Country of Publication:
United States
Language:
English

Similar Records

FPGA Trigger System to Run Klystrons
Technical Report · Wed Aug 25 00:00:00 EDT 2010 · OSTI ID:992940

Support for development of a custom VLSI and FPGA logic chips based on a VHDL top-down design approach. Final report
Technical Report · Wed Jun 01 00:00:00 EDT 1994 · OSTI ID:10159138

First-level trigger processor for the ZEUS calorimeter
Journal Article · Fri Nov 30 23:00:00 EST 1990 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) · OSTI ID:5687714

Related Subjects