Axial Ge/Si nanowire heterostructure tunnel FETs.
- Los Alamos National Laboratory
Axial Ge/Si heterostructure nanowires (NWs) allow energy band-edge engineering along the axis of the NW, which is the charge transport direction, and the realization of asymmetric devices for novel device architectures. This work reports on two significant advances in the area of heterostructure NWs and tunnel FETs: (i) the realization of 100% compositionally modulated Si/Ge axial heterostructure NWs with lengths suitable for device fabrication and (ii) the design and implementation of Schottky barrier tunnel FETs on these NWs for high-on currents and suppressed ambipolar behavior. Initial prototype devices with 10 nm PECVD SiN{sub x} gate dielectric resulted in a very high current drive in excess of 100 {micro}A/{micro}m (I/{pi}D) and 10{sup 5} I{sub on}/I{sub off} ratios. Prior work on the synthesis of Ge/Si axial NW heterostructures through the VLS mechanism have resulted in axial Si/Si{sub 1-x}Ge{sub x} NW heterostructures with x{sub max} {approx} 0.3, and more recently 100% composition modulation was achieved with a solid growth catalyst. In this latter case, the thickness of the heterostructure cannot exceed few atomic layers due to the slow axial growth rate and concurrent radial deposition on the NW sidewalls leading to a mixture of axial and radial deposition, which imposes a big challenge for fabricating useful devices form these NWs in the near future. Here, we report the VLS growth of 100% doping and composition modulated axial Ge/Si heterostructure NWs with lengths appropriate for device fabrication by devising a growth procedure that eliminates Au diffusion on the NW sidewalls and minimizes random kinking in the heterostructure NWs as deduced from detailed microscopy analysis. Fig. 1 a shows a cross-sectional SEM image of epitaxial Ge/Si axial NW heterostructures grown on a Ge(111) surface. The interface abruptness in these Ge/Si heterostructure NWs is of the order of the NW diameter. Some of these NWs develop a crystallographic kink that is {approx}20{sup o} off the <111> axis at about 300 nm away from the Ge/Si interface. This provides a natural marker for placing the gate contact electrodes and gate metal at appropriate location for desired high-on current and reduced ambipolarity as shown in Fig. 2. The 1D heterostructures allow band-edge engineering in the transport direction, not easily accessible in planar devices, providing an additional degree of freedom for designing tunnel FETs (TFETs). For instance, a Ge tunnel source can be used for efficient electron/hole tunneling and a Si drain can be used for reduced back-tunneling and ambipolar behavior. Interface abruptness on the other hand (particularly for doping) imposes challenges in these structures and others for realizing high performance TFETs in p-i-n junctions. Since the metal-semiconductor contacts provide a sharp interface with band-edge control, we use properly designed Schottky contacts (aided by 3D Silvaco simulations) as the tunnel barriers both at the source and drain and utilize the asymmetry in the Ge/Si channel bandgap to reduce ambipolar transport behavior generally observed in TFETs. Fig. 3 shows the room-temperature transfer curves of a Ge/Si heterostructure TFET (H-TFET) for different V{sub DS} values showing a maximum on-current of {approx}7 {micro}A, {approx}170 mV/decade inverse subthreshold slope and 5 orders of magnitude I{sub on}/I{sub off} ratios for all V{sub DS} biases considered here. This high on-current value is {approx}1750 X higher than that obtained with Si p-i-n{sup +} NW TFETs and {approx}35 X higher than that obtained with CNT TFET. The I{sub on}/I{sub off} ratio and inverse subthreshold slope compare favorably to that of Si {approx} 10{sup 3} I{sub on}/I{sub off} and {approx} 800 mV/decade SS{sup -1} but lags behind those of CNT TFET due to poor PECVD nitride gate oxide quality ({var_epsilon}{sub r} {approx} 3-4). The asymmetry in the Schottky barrier heights used here eliminates the stringent requirements of abrupt doped interfaces used in p-i-n based TFETs, which is hard to achieve both in thin-film and in NW growth. These initial promising results are expected to be further improved by using a high-k gate dielectric.
- Research Organization:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 990955
- Report Number(s):
- SAND2010-1976C; TRN: US201020%%705
- Resource Relation:
- Conference: Proposed for presentation at the Device Research Conference held June 21-23, 2010 in South Bend, IN.
- Country of Publication:
- United States
- Language:
- English
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