Noise impact of single-event upsets on an FPGA-based digital filter
Conference
·
OSTI ID:989821
- Los Alamos National Laboratory
- BYU
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output.
- Research Organization:
- Los Alamos National Laboratory (LANL)
- Sponsoring Organization:
- DOE
- DOE Contract Number:
- AC52-06NA25396
- OSTI ID:
- 989821
- Report Number(s):
- LA-UR-09-03658; LA-UR-09-3658
- Country of Publication:
- United States
- Language:
- English
Similar Records
The Reliability of FPGA circuit designs in the presence of radiation induced configuration upsets
Evaluation of power costs in applying TMR to FPGA designs.
SEU mitigation for half-latches in Xilinx Virtex FPGAs
Conference
·
Tue Dec 31 23:00:00 EST 2002
·
OSTI ID:976614
Evaluation of power costs in applying TMR to FPGA designs.
Conference
·
Wed Dec 31 23:00:00 EST 2003
·
OSTI ID:977895
SEU mitigation for half-latches in Xilinx Virtex FPGAs
Journal Article
·
Sun Nov 30 23:00:00 EST 2003
· IEEE Transactions on Nuclear Science
·
OSTI ID:819344