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Title: System and method for adaptively deskewing parallel data signals relative to a clock

Patent ·
OSTI ID:985407

A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
W-7405-ENG-48
Assignee:
Silicon Graphics, Inc. (Sunnyvale, CA)
Patent Number(s):
7,433,441
Application Number:
11/405,387
OSTI ID:
985407
Country of Publication:
United States
Language:
English

References (3)

A Cmos Serial Link For 1 Gbaud Fully Duplexed Data Communication conference June 1994
Time-domain response of multiconductor transmission lines journal June 1987
A 900 Mb/s bidirectional signaling scheme journal January 1995