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Title: Low latency counter event indication

Abstract

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

Inventors:
 [1];  [2]
  1. Mount Kisco, NY
  2. Chappaqua, NY
Publication Date:
Research Org.:
International Business Machines Corporation (Armonk, NY)
Sponsoring Org.:
USDOE
OSTI Identifier:
984518
Patent Number(s):
7,426,253
Application Number:
11/507,308
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
47 OTHER INSTRUMENTATION

Citation Formats

Gara, Alan G, and Salapura, Valentina. Low latency counter event indication. United States: N. p., 2008. Web.
Gara, Alan G, & Salapura, Valentina. Low latency counter event indication. United States.
Gara, Alan G, and Salapura, Valentina. Tue . "Low latency counter event indication". United States. doi:. https://www.osti.gov/servlets/purl/984518.
@article{osti_984518,
title = {Low latency counter event indication},
author = {Gara, Alan G and Salapura, Valentina},
abstractNote = {A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 16 00:00:00 EDT 2008},
month = {Tue Sep 16 00:00:00 EDT 2008}
}

Patent:

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