Metropolitan Road Traffic Simulation on FPGAs.
- Justin L.
- Henning S.
- Anders A.
- Maya
This work demonstrates that road traffic simulation of entire metropolitan areas is possible with reconfigurable supercomputing that combines 64-bit microprocessors and FPGAs in a high bandwidth, low latency interconnect. Previously, traffic simulation on FPGAs was limited to very short road segments or required a very large number of FPGAs. Our data streaming approach overcomes scaling issues associated with direct implementations and still allows for high-level parallelism by dividing the data sets between hardware and software across the reconfigurable supercomputer. Using one FPGA on the Cray XD1 supercomputer, we are able to achieve a 34.4 x speed up over the AMD microprocessor. System integration issues must be optimized to exploit this speedup in the overall simulation.
- Research Organization:
- Los Alamos National Laboratory
- Sponsoring Organization:
- DOE
- OSTI ID:
- 977943
- Report Number(s):
- LA-UR-05-0333
- Country of Publication:
- United States
- Language:
- English
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