Monte Carlo radiative heat transfer simulation on a reconfigurable computer

Conference · Wed Dec 31 23:00:00 EST 2003

DOI:https://doi.org/10.1007/978-3-540-30117-2_12· OSTI ID:977513

Gokhale, M ^[1]; Ahrens, C M ^[2]; Frigo, J ^[3]; Minnich, R G ^[4]; L, Tripp J ^[5]

---

1. Maya
2. Christine Marie
3. Janette
4. Ronald G.
5. Justin L.

Recently, the appearance of very large (3-10M gate) FPGAs with embedded arithmetic units has opened the door to the possibility of floating point computation on these devices. While previous researchers have described peak performance or kernel matrix operations, there is as yet little experience with mapping an application-specific floating point pipeline onto FPGAs. In this work, we port a supercomputer application benchmark onto Xilinx Virtex II and II Pro FPGAs and compare performance with comparable microprocessor implementation. Our results show that this application-specific pipeline, with 12 multiply, 10 add/subtract, one divide, and two compare modules of single precision floating point data type, shows speedup of 1.6x-1.7x. We analyze the trade-offs between hardware and software 'sweet spots' to characterize the algorithms that will perform well on current and future FPGA architectures.

• Research Organization: Los Alamos National Laboratory
• Sponsoring Organization: DOE
• OSTI ID: 977513
• Report Number(s): LA-UR-04-1807
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
ACCURACY
ALGORITHMS
BENCHMARKS
COMPUTERS
DOORS
HEAT TRANSFER
IMPLEMENTATION
KERNELS
MICROPROCESSORS
PERFORMANCE
PIPELINES
SIMULATION
SUPERCOMPUTERS