A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

Conference · Tue Jan 01 04:00:00 EST 2008

DOI:https://doi.org/10.1109/AUTEST.2008.4662621· OSTI ID:957712

Quinn, Heather M ^[1]; Graham, Paul S ^[1]; Morgan, Keith S ^[1]; Caffrey, Michael P ^[1]

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1. Los Alamos National Laboratory

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

• Research Organization: Los Alamos National Laboratory (LANL)
• Sponsoring Organization: DOE
• DOE Contract Number: AC52-06NA25396
• OSTI ID: 957712
• Report Number(s): LA-UR-08-04246; LA-UR-08-4246
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING
ACCELERATORS
DESIGN
GOLD
RADIATIONS
REDUNDANCY
SIMULATION
TESTING