The chip-scale atomic clock : prototype evaluation.

Conference · Sat Dec 01 00:00:00 EST 2007

OSTI ID:946267

Mescher, Mark ^[1]; Varghese, Mathew ^[1]; Lutwak, Robert ^[2]; Serkland, Darwin Keith; Tepolt, Gary ^[1]; Geib, Kent Martin; Leblanc, John ^[1]; Peake, Gregory Merwin; Rashid, Ahmed ^[2]

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1. Charles Stark Draper Laboratory, Cambridge, MA
2. Symmetricom - Technology Realization Center, Beverly, MA

The authors have developed a chip-scale atomic clock (CSAC) for applications requiring atomic timing accuracy in portable battery-powered applications. At PTTI/FCS 2005, they reported on the demonstration of a prototype CSAC, with an overall size of 10 cm{sup 3}, power consumption > 150 mW, and short-term stability sy(t) < 1 x 10-9t-1/2. Since that report, they have completed the development of the CSAC, including provision for autonomous lock acquisition and a calibrated output at 10.0 MHz, in addition to modifications to the physics package and system architecture to improve performance and manufacturability.

• Research Organization: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 946267
• Report Number(s): SAND2007-7800C; TRN: US200903%%277
• Resource Relation: Conference: Proposed for presentation at the Precise Time and Time Interval (PTTI) 2007 Meeting held November 26-29, 2007 in Long Beach, CA.
• Country of Publication: United States
• Language: English

Related Subjects

47 OTHER INSTRUMENTATION
ATOMIC CLOCKS
MINIATURIZATION
PERFORMANCE
DESIGN