Hybrid MOSFET/Driver for Ultra-Fast Switching

Conference · Fri Jul 11 00:00:00 EDT 2008

OSTI ID:934743

Tang, T; Burkhart, C

The ultra-fast switching of power MOSFETs, in {approx}1ns, is very challenging. This is largely due to the parasitic inductance that is intrinsic to commercial packages used for both MOSFETs and drivers. Parasitic gate and source inductance not only limit the voltage rise time on the MOSFET internal gate structure but can also cause the gate voltage to oscillate. This paper describes a hybrid approach that substantially reduces the parasitic inductance between the driver and MOSFET gate as well as between the MOSFET source and its external connection. A flip chip assembly is used to directly attach the die-form power MOSFET and driver on a PCB. The parasitic inductances are significantly reduced by eliminating bond wires and minimizing lead length. The experimental results demonstrate ultra-fast switching of the power MOSFET with excellent control of the gate-source voltage.

• Research Organization: Stanford Linear Accelerator Center (SLAC)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC02-76SF00515
• OSTI ID: 934743
• Report Number(s): SLAC-PUB-13269
• Conference Information: Presented at2008 IEEE International Power Modulator Conference, Las Vegas, NV, 5/27/2008-5/31/2008
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
INDUCTANCE
MITIGATION
MOSFET
Other
ENG
PULSE RISE TIME
SWITCHES