SVX4 User's manual
We present and describe the operation of the SVX4 chip. The SVX4 is a custom 128-channel analog to digital converter chip used by D0 and CDF in Run IIb to read out their respective silicon strip detectors. Each channel consists of an integrator (Front-End device, or FE) and a digitize/readout section (Back-End device, or BE). The input to each channel is sampled and temporarily stored in its own storage capacitor. Upon receiving a trigger signal, the relevant pipeline cell is reserved. Subsequent signals cause reserved cells to be digitized by a 128 parallel channel Wilkinson type 8-bit ADC, and then readout in byte-serial mode with optional zero suppression (sparsification). Salient features include (1) operation in either D0 mode or CDF mode (CDF mode features ''dead timeless operation'' or continued acquisition during digitization and readout) with an additional mixed mode of operation, (2) adjustable, loadable control parameters, including the integrator bandwidth and ADC polarity (only one input charge polarity will be used for Run IIb, but this feature remains for diagnostic purposes), (3) sparsified readout with nearest neighbor logic, (4) built-in charge injection with the ability for external voltage overriding for testing and calibration, and (5) a channel mask that is used for either charge injection or for masking of channels with excessive DC current input during chip operation. This document is meant to familiarize the user with the functionality of the SVX4 and goes on to include specifications, pin outs, timings and electrical information. Additional information on the SVX4 can be found in Ref [1].
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-76CH03000
- OSTI ID:
- 879061
- Report Number(s):
- FERMILAB-TM-2318-E; TRN: US0605051
- Country of Publication:
- United States
- Language:
- English
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