Preliminary test results for the SVX4

Technical Report · Wed Jun 01 04:00:00 EDT 2005

DOI:https://doi.org/10.2172/875568· OSTI ID:875568

Christofek, L; Hanagaki, K; Rapidis, P; Utes, M

We present and summarize the preliminary test results for SVX4 chip testing. There are presently two versions of the SVX4. Version 2 has on-chip bypassing and Version 1 does not. The on-chip bypassing is a layer of transistors under the front-end analog pipeline that acts as a bypassing capacitor for the voltage supply. Its size is about a microfarad. We aggressively choose to test Version 2 because of this feature. The feature is advantageous for hybrid design because it eliminates the need for an additional passive component on the hybrid itself by placing it on the actual SVX4 die. Also, the SVX4 was designed to operate in two modes: D. and CDF. One can set which mode the chip will operate by placing a jumper in the proper position on the SVX4 chip carrier. In either mode, the chip can either use the operating parameters from the shift register or the shadow register. Similarly, this is selected by placing a jumper on the SVX4 chip carrier. This chip has this feature because it was unknown whether the new design of the shadow register would be operable. The shadow register is also call the SEU register or Single Event Upset register. An introduction into the functionality of the chip and an explanation on the difference between D. and CDF mode can be found in the SVX4 User's Manual [1].

• Research Organization: Fermi National Accelerator Laboratory (FNAL), Batavia, IL
• Sponsoring Organization: USDOE
• DOE Contract Number: AC02-76CH03000
• OSTI ID: 875568
• Report Number(s): FERMILAB-TM-2316-E
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS
AVAILABILITY
CAPACITORS
DESIGN
Experiment-HEP
FERMILAB COLLIDER DETECTOR
PIPELINES
TESTING
TRANSISTORS