Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

Patent · Wed Jan 01 04:00:00 EST 2003

OSTI ID:875136

Toet, Daniel ^[1]; Sigmon, Thomas W ^[2]

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1. Mountain View, CA
2. Albuquerque, NM

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA
• DOE Contract Number: W-7405-ENG-48
• Assignee: The Regents of the University of California (Oakland, CA)
• Patent Number(s): US 6541316
• OSTI ID: 875136
• Country of Publication: United States
• Language: English

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