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Offset-free rail-to-rail derandomizing peak detect-and-hold circuit

Patent ·
OSTI ID:875012

A peak detect-and-hold circuit eliminates errors introduced by conventional amplifiers, such as common-mode rejection and input voltage offset. The circuit includes an amplifier, three switches, a transistor, and a capacitor. During a detect-and-hold phase, a hold voltage at a non-inverting in put terminal of the amplifier tracks an input voltage signal and when a peak is reached, the transistor is switched off, thereby storing a peak voltage in the capacitor. During a readout phase, the circuit functions as a unity gain buffer, in which the voltage stored in the capacitor is provided as an output voltage. The circuit is able to sense signals rail-to-rail and can readily be modified to sense positive, negative, or peak-to-peak voltages. Derandomization may be achieved by using a plurality of peak detect-and-hold circuits electrically connected in parallel.

Research Organization:
Brookhaven National Laboratory (BNL), Upton, NY
DOE Contract Number:
AC02-98CH10886
Assignee:
Brookhaven Science Associates LLC (Upton, NY)
Patent Number(s):
US 6512399
OSTI ID:
875012
Country of Publication:
United States
Language:
English

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