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Title: Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

Patent ·
OSTI ID:871994
 [1]
  1. 1304 Onava Ct., NE., Albuquerque, NM 87112
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A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Research Organization:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
DOE Contract Number:
AC04-94AL85000
Assignee:
Seager, Carleton H. (1304 Onava Ct., NE., Albuquerque, NM 87112);Evans, Jr., Joseph Tate (13609 Verbena Pl., NE., Albuquerque, NM 87112)
Patent Number(s):
US 5840620
OSTI ID:
871994
Country of Publication:
United States
Language:
English

References (4)

Effect of hydrogen plasma treatment on transparent conducting oxides journal August 1986
Annealing effects in indium oxide films prepared by reactive evaporation journal January 1985
Properties of Sn‐doped In 2 O 3 by reactive magnetron sputtering and subsequent annealing journal July 1987
Effects of heat treatment and ion doping of indium oxide journal June 1989

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method
restoring
resistance
indium
oxide
semiconductors
heating
sealed
structures
counteracting
increases
resistivity
encountered
resistive
layers
subjected
temperature
annealing
steps
semiconductor
device
fabrication
utilizes
recovery
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returns
layer
original
caused
increase
anneal
comprises
100
degree
300
period
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depends
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dielectric
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method utilizes
indium oxide
dielectric layer
oxide layer
semiconductor device
annealing steps
comprises heating
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annealing temperature
oxide semiconductor
temperature annealing
temperature anneal
resistive layer
resistive layers
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