Lambda network having 2.sup.m-1 nodes in each of m stages with each node coupled to four other nodes for bidirectional routing of data packets between nodes

Lambda network having 2.sup.m-1 nodes in each of m stages with each node coupled to four other nodes for bidirectional routing of data packets between nodes

Patent · Sun Jan 01 04:00:00 EST 1995

OSTI ID:870187

The Lambda network is a single stage, packet-switched interprocessor communication network for a distributed memory, parallel processor computer. Its design arises from the desired network characteristics of minimizing mean and maximum packet transfer time, local routing, expandability, deadlock avoidance, and fault tolerance. The network is based on fixed degree nodes and has mean and maximum packet transfer distances where n is the number of processors. The routing method is detailed, as are methods for expandability, deadlock avoidance, and fault tolerance.

Research Organization:: AT & T CORP

DOE Contract Number:: AC04-76DP00789

Assignee:: Napolitano, Jr., Leonard M. (825 El Quanito Dr., Danville, CA 94526)

Patent Number(s):: US 5471623

OSTI ID:: 870187

Country of Publication:: United States

Language:: English

References (10)

The cube-connected cycles: a versatile network for parallel computation Preparata, Franco P.; Vuillemin, Jean Communications of the ACM, Vol. 24, Issue 5 https://doi.org/10.1145/358645.358660	journal	May 1981
Using the multistage cube network topology in parallel supercomputers Siegel, H. J.; Nation, W. G.; Kruskal, C. P. Proceedings of the IEEE, Vol. 77, Issue 12 https://doi.org/10.1109/5.48833	journal	January 1989
The Lens Interconnection Strategy Finkel, R. A.; Solomon, Marvin IEEE Transactions on Computers, Vol. C-30, Issue 12, p. 960-965 https://doi.org/10.1109/TC.1981.1675735	journal	December 1981
A Loop-Structured Switching Network Wong, F. S.; Ito, M. R. IEEE Transactions on Computers, Vol. C-33, Issue 5, p. 450-455 https://doi.org/10.1109/TC.1984.1676462	journal	May 1984
An Algorithm for Detecting and Resolving Store-and-Forward Deadlocks in Packet-Switched Networks Chan, Cheung-Wing; Yum, Tak-Shing IEEE Transactions on Communications, Vol. 35, Issue 8, p. 801-807 https://doi.org/10.1109/TCOM.1987.1096856	journal	August 1987
Prevention of Deadlocks in Packet-Switched Data Transport Systems Gunther, K. IEEE Transactions on Communications, Vol. 29, Issue 4 https://doi.org/10.1109/TCOM.1981.1095021	journal	April 1981
A fault tolerant massively parallel processing architecture Balasubramanian, Vijay; Banerjee, Prithviraj Journal of Parallel and Distributed Computing, Vol. 4, Issue 4 https://doi.org/10.1016/0743-7315(87)90025-6	journal	August 1987
The Universality of the Shuffle-Exchange Network Wu, Chuan-Lin; Feng, Tse-Yun IEEE Transactions on Computers, Vol. C-30, Issue 5, p. 324-332 https://doi.org/10.1109/TC.1981.1675790	journal	May 1981
A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks Gelernter, David IEEE Transactions on Computers, Vol. C-30, Issue 10, p. 709-715 https://doi.org/10.1109/TC.1981.1675690	journal	October 1981
Prevention of Store-and-Forward Deadlock in Computer Networks Gopal, I. IEEE Transactions on Communications, Vol. 33, Issue 12 https://doi.org/10.1109/TCOM.1985.1096253	journal	January 1985

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/709/370/
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avoidance
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data
deadlock
degree
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detailed
distances
distributed
expandability
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interprocessor
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m-1
maximum
mean
memory
method
methods
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processor
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single
single stage
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Lambda network having 2.sup.m-1 nodes in each of m stages with each node coupled to four other nodes for bidirectional routing of data packets between nodes

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References (10)

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