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Title: Allocating application to group of consecutive processors in fault-tolerant deadlock-free routing path defined by routers obeying same rules for path selection

Patent ·
OSTI ID:1012604
 [1];  [1];  [2];  [3]
  1. Albuquerque, NM
  2. East Northport, NY
  3. Urbana, IL
+ Show Author Affiliations

In a multiple processor computing apparatus, directional routing restrictions and a logical channel construct permit fault tolerant, deadlock-free routing. Processor allocation can be performed by creating a linear ordering of the processors based on routing rules used for routing communications between the processors. The linear ordering can assume a loop configuration, and bin-packing is applied to this loop configuration. The interconnection of the processors can be conceptualized as a generally rectangular 3-dimensional grid, and the MC allocation algorithm is applied with respect to the 3-dimensional grid.

Research Organization:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Number(s):
7,565,657
Application Number:
11/110,206
OSTI ID:
1012604
Country of Publication:
United States
Language:
English

References (6)

Noncontiguous processor allocation algorithms for mesh-connected multicomputers journal July 1997
Algorithmic support for commodity-based parallel computing systems. report October 2003
Communication patterns and allocation strategies conference January 2004
Processor allocation on Cplant: achieving general processor locality using one-dimensional allocation strategies conference January 2002
Contention-free 2D-mesh cluster allocation in hypercubes journal January 1995
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks journal May 1987

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Related Subjects

97 MATHEMATICS AND COMPUTING