High performance static latches with complete single event upset immunity
Patent
·
OSTI ID:869264
- Albuquerque, NM
An asymmetric response latch providing immunity to single event upset without loss of speed. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states.
- Research Organization:
- AT & T CORP
- DOE Contract Number:
- AC04-76DP00789
- Assignee:
- United States of America as represented by United States (Washington, DC)
- Patent Number(s):
- US 5307142
- OSTI ID:
- 869264
- Country of Publication:
- United States
- Language:
- English
Comparison of Analytical Models and Experimental Results for Single Event Upset in CMOS SRAMs
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journal | January 1983 |
An SEU-hardened CMOS data latch design
|
journal | January 1988 |
An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM
|
journal | January 1987 |
A proposed new structure for SEU immunity in SRAM employing drain resistance
|
journal | November 1987 |
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