High performance static latches with complete single event upset immunity
Patent
·
OSTI ID:5037725
An asymmetric response latch providing immunity to single event upset without loss of speed is described. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states. 5 figures.
- DOE Contract Number:
- AC04-76DP00789
- Assignee:
- Dept. of Energy, Washington, DC (United States)
- Patent Number(s):
- A; US 5307142
- Application Number:
- PPN: US 7-793084
- OSTI ID:
- 5037725
- Country of Publication:
- United States
- Language:
- English
Similar Records
High performance static latches with complete single event upset immunity
Single event upset hardening techniques
Considerations for single-event immune VLSI logic
Patent
·
Fri Dec 31 23:00:00 EST 1993
·
OSTI ID:869264
Single event upset hardening techniques
Conference
·
Sun Dec 31 23:00:00 EST 1989
·
OSTI ID:6427281
Considerations for single-event immune VLSI logic
Conference
·
Fri Dec 31 23:00:00 EST 1982
·
OSTI ID:5988019