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Method of producing strained-layer semiconductor devices via subsurface-patterning

Patent ·
OSTI ID:868844
 [1]
  1. Albuquerque, NM
+ Show Author Affiliations
A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.
Research Organization:
AT & T CORP
DOE Contract Number:
AC04-76DP00789
Assignee:
United States of America as represented by United States (Washington, DC)
Patent Number(s):
US 5225368
OSTI ID:
868844
Country of Publication:
United States
Language:
English

References (1)

Excess stress and the stability of strained heterostructures journal September 1988

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Related Subjects

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electrical
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predetermined
predetermined thickness
producing
relaxation
relaxed
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semiconductor
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stabilizes
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strained
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subsequently
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surface feature
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via
whereby
whereby dislocation