Final Report and Documentation for the PLD11 Multipurpose Programmable Logic VME Board Design
- Sandia National Laboratories
The PLD11 board is a 9U VME board containing 11 Altera 10K100 Programmable Logic Devices, controlled impedance clock tree, VME interface, programming inteface, 0C3 (155 Mbps) interface and serial port. The 11 Altera 10K100 Programmable Logic Devices arranged to provide four 96 bit wide buses for a total of 384 parallel digital data lines in and out of the board that can operate up to 100 Mhz for a aggrigate throughput of 38.4 Gpbs. The 14.44" X 15.75" board has over 1.1 million programmable gates that can be programmed through a serial interace. The board contains a clock reference and 50 ohm clock distribution tree that can drive each of the eleven 10K100 devices with two critically timed clock references. Five external clock references can be used to drive five additional PLD 11 boards for a total of six boards operating all from the same synchronous clock reference. A system of six boards provides just under 7 million programmable gates.
- Research Organization:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 8369
- Report Number(s):
- SAND99-0914; ON: DE00008369
- Country of Publication:
- United States
- Language:
- English
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