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Title: Flexible programmable logic module

Abstract

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

Inventors:
 [1];  [1];  [1]
  1. (Albuquerque, NM)
Publication Date:
Research Org.:
SANDIA CORP
OSTI Identifier:
874139
Patent Number(s):
US 6323679
Assignee:
Sandia Corporation (Albuquerque, NM) SNL
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
flexible; programmable; logic; module; circuit; vme; board; containing; plurality; devices; plds; controlled; impedance; clock; tree; interconnecting; buses; arranged; permit; systolic; processing; offering; wide; data; nodes; contains; reference; distribution; drive; critically; timed; references; external; additional; modules; operating; synchronous; programmable logic; /326/

Citation Formats

Robertson, Perry J., Hutchinson, Robert L., and Pierson, Lyndon G. Flexible programmable logic module. United States: N. p., 2001. Web.
Robertson, Perry J., Hutchinson, Robert L., & Pierson, Lyndon G. Flexible programmable logic module. United States.
Robertson, Perry J., Hutchinson, Robert L., and Pierson, Lyndon G. Mon . "Flexible programmable logic module". United States. doi:. https://www.osti.gov/servlets/purl/874139.
@article{osti_874139,
title = {Flexible programmable logic module},
author = {Robertson, Perry J. and Hutchinson, Robert L. and Pierson, Lyndon G.},
abstractNote = {The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Mon Jan 01 00:00:00 EST 2001},
month = {Mon Jan 01 00:00:00 EST 2001}
}

Patent:

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