Performance of Front-End Readout System for PHENIX RICH
Conference
·
OSTI ID:771520
- ORNL
A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.
- Research Organization:
- Oak Ridge National Lab., TN (US)
- Sponsoring Organization:
- USDOE Office of Science (US)
- DOE Contract Number:
- AC05-00OR22725
- OSTI ID:
- 771520
- Report Number(s):
- P00-107384
- Country of Publication:
- United States
- Language:
- English
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