Performance of Front-End Readout System for PHENIX RICH

Conference · Mon Nov 15 00:00:00 EST 1999

OSTI ID:771520

Oyama, K; Hamagaki, H; Nishimura, S; Shigaki, K; Hayano, R S; Hibino, M; Kametani, S; Kikuchi, J; Matsumoto, T; Sakaguchi, T; Ebisu, K; Hara, H; Tanaka, Y; Ushiroda, T; Moscone, C G; Wintenberg, A L; Young, G R

A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

• Research Organization: Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: USDOE Office of Science (US)
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 771520
• Report Number(s): P00-107384; TRN: US0100515
• Resource Relation: Conference: 7th Int. Conf. on Instrumentation for Colliding Beam Physics, Hamamatsu (JP), 11/15/2000--11/19/2000; Other Information: PBD: 15 Nov 1999
• Country of Publication: United States
• Language: English

Related Subjects

73 NUCLEAR PHYSICS AND RADIATION PHYSICS
COLLIDING BEAMS
PERFORMANCE
PHYSICS
READOUT SYSTEMS