Synchronous semiconductor memory device
Patent
·
OSTI ID:7159617
This patent describes a synchronous semiconductor memory device. It comprises: first latch means for latching a write command in synchronism with clock signal; second latch means for latching a write data in synchronism with the clock signal and for outputting two write process signals based on the write data latched thereby; pulse generating means for generating an internal write pulse signal based on the write command latched by the first latch means. The internal write pulse signal having a semiconductor memory device; write control means supplied with the internal write pulse signal and the write process signals for controlling write and read operations of the synchronous semiconductor memory device; memory means for storing the write data latched by the second latch means; and noise preventing means coupled to the second latch means and the write control means for supplying the write process signals to the write control means only in the write mode responsive to the internal write pulse signal and for setting the write process signals to fixed potentials during a time other than the write mode.
- Assignee:
- Fujitsu Limited, Kawasaki
- Patent Number(s):
- US 4882712; A--
- OSTI ID:
- 7159617
- Country of Publication:
- United States
- Language:
- English
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